Abstract: Embodiments of the present disclosure provide a method, a coalescing configuration engine, a coalescing configuration tool and a file system for a storage system, and comprises at least one initiator, each initiator accessing a corresponding storage space in the storage system via at least one virtual logic unit number LUN by executing in parallel a plurality of configuration operations, wherein each configuration operation is used to configure a mapping relationship between the at least one virtual LUN and the at least one initiator.

Abstract: An apparatus may include a processor component caused to: generate map entries in map data descriptive of encrypted data blocks within a data file; use first map block encryption data to encrypt a first map extension of the map data; transmit the encrypted first map extension for storage within the data file; store the first map block encryption data within the second map extension; use second map block encryption data to encrypt a second map extension of the map data after storage of the first map block encryption data therein; transmit encrypted second map extension for storage within the data file; store the second map block encryption data within the map base; use third map block encryption data to encrypt a map base of the map data after storage of the second map block encryption data therein; and transmit the encrypted map base for storage within the data file.

Abstract: An apparatus includes a processor component caused to: retrieve metadata of organization of data within a data set, and map data of organization of data blocks within a data file; receive indications of which node devices are available to perform a processing task with a data set portion; and in response to the data set including partitioned data, compare the quantities of available node devices and of the node devices last involved in storing the data set. In response to a match, for each map data map entry: retrieve a hashed identifier for a data sub-block, and a size for each of the data sub-blocks within the corresponding data block; divide the hashed identifier by the quantity of available node devices; compare the modulo value to a designation assigned to each of the available node devices; and provide a pointer to the available node device assigned the matching designation.

Abstract: A storage control device that includes processing circuitry that receives second access instructions of a plurality of series generated based on a first access instruction for instructing writing of data in a first storage or reading of data from the first storage, through a plurality of channels, the storage control device being connected to a controller configured to perform writing of data in the first storage or reading of data from the first storage according to an instruction for accessing the first storage, reassembles the first access instruction based on the second access instructions of the plurality of series received by the processing circuitry, and outputs the first access instruction reassembled by the processing circuitry to the controller.

Abstract: A system and method is disclosed for providing zero data in response to a host data read directed to a logical address that is not associated with valid data. The system may be a non-volatile memory system including non-volatile memory and a controller configured to determine whether a logical address in a read command is associated with valid data. The controller may be configured to generate, store in non-volatile memory and retrieve from that non-volatile memory a zero data entry. The controller may also be configured to include any associated encryption key or logical address in the generation of the zero data in order to satisfy data path protection and/or encryption requirements for the non-volatile memory system. Storage and retrieval of the zero data may be via the non-volatile memory array or only the data latches of the non-volatile memory.

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect. In response to a load-and-reserve request from a first processor core, a first cache memory supporting the first processor core issues on the system interconnect a memory access request for a target cache line of the load-and-reserve request. Responsive to the memory access request and prior to receiving a systemwide coherence response for the memory access request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the memory access request. In response to the early indication and prior to receiving the systemwide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.

Abstract: A method of operating a data processing system comprises maintaining record of a set of processing passes to be performed by processing pass circuitry of the data processing system. The method comprises performing cycles of operation in which it is considered whether or not the data required for a subset of processing passes is stored in a local cache. The subset of processing passes that is considered in a subsequent scan of the record comprises at least one processing pass that was not considered in the previous scan of the record, regardless of whether or not the data considered in the previous scan is determined as being stored in the cache. The method provides an efficient way to identify processing passes that are ready to be performed.

Abstract: An application processor and a mobile apparatus are provided. The application processor includes a memory device configured to store data based upon a plurality of address mapping formats, an address mapping table configured to store information on one of the address mapping formats to access the data, a system bus configured to generate a second address based upon a first address to access the data and the address mapping table and a data processing device configured to receive the data according to the second address through the system bus.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, and a controller which writes a first data table including a first data group including a first logical address corresponding to a first physical and a first count value and a second data group including a second logical address corresponding to a second physical address and a second count value, to the volatile memory, reads the first data table when a third logical address is requested to be read, compares the first count value and the second count value with each other, and rewrites the first data group or the second data group to a third data group including a third logical address based on a result of the comparison.

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and an interconnect fabric. In response to a first cache memory snooping on the interconnect fabric a request of an interconnect operation of a second cache memory, the first cache memory allocates a snoop machine to service the request. Responsive to the snoop machine completing its processing of the request and prior to the first cache memory receiving a systemwide coherence response of the interconnect operation, the first cache memory allocates an entry in a data structure to handle completion of processing for the interconnection operation and deallocates the snoop machine. The entry of the data structure protects transfer of coherence ownership of a target cache line from the first cache memory to the second cache memory during a protection window extending at least until the systemwide coherence response is received.

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies. A first cache memory in a first vertical cache hierarchy issues on the system interconnect a request for a target cache line. Responsive to the request and prior to receiving a systemwide coherence response for the request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the request. In response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, the first cache memory initiates processing to install the target cache line in the first cache memory.

Abstract: An object based storage cluster includes at least one Data Storage Device (DSD) with a plurality of media portions for storing data. Media mapping information is received from the at least one DSD with the media mapping information indicating addresses assigned to each media portion of the plurality of media portions. Each media portion of the plurality of media portions is identified as a separate Object Storage Device (OSD) in the object based storage cluster using the media mapping information.

Abstract: The present invention provides a data storage system and method. A controller is connected to a plurality of disk arrays, and each disk array is provided with a data protection unit for data protection. When one disk drive of one of the disk arrays is damaged, this disk array is defined as a damaged disk array, while other disk arrays without disk drives being damaged are defined as at least one normal disk array. The controller stops to write a new written data into the damaged disk array, while write the new written data into the normal disk arrays. The new written data will be protected by the data protection units of the normal disk arrays. Thereby, continuous data protection for the new written data by the data protection units together with preservation of storage performance of the system, after the disk drive is damaged, may be achieved.

Abstract: A method, computer program product, and/or system for performing a selection of a plurality of auxiliary storage sites in a multi-target environment in preparation for a hyper exchange are/is provided. To perform the selection, a failure is first detected with respect to a primary storage site in the multi-target environment. Then, aggregate weights are determined based on a management policy for the plurality of auxiliary storage sites. In turn, an auxiliary storage site with a first aggregate weight is selected from the plurality of auxiliary storage sites. With the auxiliary storage site selected, the hyper exchange of a plurality of systems in a multi-target environment in response to the failure is triggered from the primary storage site to the auxiliary storage site with the first aggregate weight.

Abstract: A plurality of memory modules, which may be used to form a heterogeneous memory system, are connected to a plurality of prefetchers. Each prefetcher is independently configured to prefetch information from a corresponding one of the plurality of memory modules in response to feedback from the corresponding one of the plurality of memory modules.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a basic input/output system comprising a program of instructions executable by the processor and configured to cause the processor to initialize one or more information handling resources of the information handling system. The basic input/output system may be further configured to, prior to boot of an operating system of the information handling system, initialize a virtual device controller emulating a hardware controller for controlling peripheral devices communicatively coupled to the processor, and cause the virtual device controller to interact with a driver executing on the operating system to control the peripheral devices.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a buffer, a battery and a processing circuit. The battery stores energy supplied from the outside. The processing circuit, after start of the supply of energy from the outside, starts the acceptance of a request from the outside, starts a process in accordance with the accepted request, and restricts the amount of data in the buffer referring to a voltage of the battery. The process uses the buffer.

Abstract: A non-volatile memory system may include a controller that issues data transfer commands to have data units associated with a host read request transferred from non-volatile memory to a temporary storage area before the data is sent to a host. The controller may be configured to generate a schedule that identifies when the data transfer commands are issued. The schedule may be generated according to one of a plurality of scheduling schemes, each with a different priority in having the data units transferred to the temporary storage area. Which scheduling scheme the controller selects may depend on a queue depth of a read request queue.

Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space. Instructions that modify the main address space are intercepted, storage delta packets are generated based on intercepted instructions, and the storage delta packets are sent to a service co-processor maintaining a service address space.

Abstract: According to one embodiment, a control unit writes data in a write buffer to a first semiconductor storage device, and requests the first semiconductor storage device to start a background operation. The control unit writes the data to a second semiconductor storage device, and requests the second semiconductor storage device to start a background operation. When the first semiconductor device is in a busy state because of the write operation or the background operation, the control unit reads data from either the second semiconductor storage device or the write buffer.