Abstract: Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas.

Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.

Abstract: According to an exemplary embodiment of the present inventive concept, a semiconductor device is provided as follows. An active region is disposed in one side of a gate line. A non-active region is disposed in the other side of the gate line. A jumper pattern crosses a top portion of the gate line, overlapping the active region and the non-active region. A boundary between the active region and the non-active region is underneath the gate line.

Abstract: The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor device package includes a carrier, at least one electronic component, a first magnetic layer and a second magnetic layer. The carrier has a top surface on which the electronic component is disposed. The first magnetic layer is disposed on the top surface of the carrier and encapsulates the electronic component. The second magnetic layer is disposed on the first magnetic layer and covers a top surface and a lateral surface of the first magnetic layer. A permeability of the first magnetic layer is less than a permeability of the second magnetic layer.

Abstract: A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.

Abstract: An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device, and a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. The integrated circuit structure further includes a first metal layer, with a bit-line, a CVdd line, and a first CVss line in the first metal layer, a second metal layer over the first metal layer, and a third metal layer over the second metal layer. A write word-line is in the second metal layer. A read word-line is in the third metal layer.

Abstract: The present disclosure discloses an X-ray flat-panel detector and a method for preparing the same, and a white insulating material. The X-ray flat-panel detector includes: a thin-film transistor substrate; an insulating reflection layer, which is provided on the thin-film transistor substrate and has a reflection function, wherein the insulating reflection layer is provided with a contact hole through which a source electrode of the thin-film transistor substrate is exposed; a pixel electrode, which is provided on the insulating reflection layer, wherein the pixel electrode is electrically connected to the source electrode of the thin-film transistor substrate via the contact hole; a photodiode, which covers the pixel electrode; an electrode, which is provided on the photodiode; and an X-ray conversion layer, which is provided on the electrode.

Abstract: A micromechanical structure comprises a substrate and a functional structure arranged at the substrate. The functional structure comprises a functional region which is deflectable with respect to the substrate responsive to a force acting on the functional region. The functional structure comprises a carbon layer arrangement, wherein a basis material of the carbon layer arrangement is a carbon material.

Abstract: Provided is a vertical neuromorphic devices stacked structure comprising a main gate which is formed on a substrate and has a vertical pillar shape, a main gate insulating layer stack formed on outer side surface of the main gate; a semiconductor region formed on outer side surface of the main gate insulating layer stack, a plurality of electrode layers formed on the side surface of the semiconductor region, a plurality of control gates formed on the side surface of the semiconductor region; and a plurality of control gate insulating layer stacks which are surrounding surfaces of the control gates and are formed between the control gate and the semiconductor region, and between the control gate and the electrode layer, and wherein the electrode layers and the control gates surrounded by the control gate insulating layer stack are stacked sequentially and alternately on the side surface of the semiconductor region.

Abstract: A method of forming a leadless packaged semiconductor device. First partial sawing leads is performed on a bottom side of an in-process leadless semiconductor package having a leadframe including die pad with a semiconductor chip thereon, and leads defining top and bottom surfaces and having an inner end and an outer end having a bottom corner region. Conductive bond wires connect to and extending between bond pads on the chip and respective leads, a mold compound is around the die pad, leads, chip, and conductive bond wires while exposing the bottom surface and outer end. The first sawing completely severs the leads while forming only a partial cut in the mold compound. A de-flash process is applied to the bottom side. The second sawing aligned to the partial cuts reaches the partial cuts to complete singulation of the package, wherein the second sawing does not touch the leads.

Abstract: First and second active regions are doped with different types of impurities, and extend in a first direction and spaced apart from each other in a second direction. First and third gate structures, which are on the first active region and a first portion of the isolation layer between the first and second active regions, extend in the second direction and are spaced apart from each other in the first direction. Second and fourth gate structures, which are on the second active region and the first portion, extend in the second direction, are spaced apart from each other in the first direction, and face and are spaced apart from the first and third gate structures, respectively, in the second direction. First to fourth contacts are on portions of the first to fourth gate structures, respectively. The first and fourth contacts are connected, and the second and third contacts are connected.

Abstract: A method of manufacturing a structure in a semiconductor body comprises forming a first mask above a first surface of the semiconductor body. The first mask comprises an opening surrounding a first portion of the first mask, thereby separating the first portion and a second portion of the first mask. The semiconductor body is processed through the opening at the first surface. The opening is increased by removing at least part of the first mask in the first portion while maintaining the first mask in the second portion. The semiconductor body is further processed through the opening at the first surface.

Abstract: Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: providing a structure with: a conductive region, and an inter-level dielectric (ILD) material positioned on the conductive region, wherein the ILD material includes a contact opening to the conductive region; forming a doped metal layer within the contact opening such that the doped metal layer overlies the conductive region, wherein the doped metal layer includes a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material.

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.

Abstract: A semiconductor device includes a semiconductor chip, a terminal layer, an insulation layer with an opening, a protection layer with an opening, an inner conductive member, an outer conductive member, and a conductive bonding member. The insulation layer includes a first insulation layer, and a second insulation layer opposite to the functional surface of the chip with respect to the first insulation layer. The second insulation layer includes a shield portion overlapping with the terminal layer in plan view, and a retracted portion not overlapping with the terminal layer in plan view. A back surface of the retracted portion of the second insulation layer is more distant from the functional surface in a z-direction than is the main surface of the terminal layer that is opposite to the functional surface.

Abstract: The present invention generally relates to a MEMS DVC. The MEMS DVC has an RF electrode and is formed above a CMOS substrate. To reduce noise in the RF signal, a poly-resistor that is connected between a waveform controller and the electrodes of the MEMS element, may be surrounded by an isolated p-well or an isolated n-well. The isolated well is coupled to an RF ground shield that is disposed between the poly-resistor and the MEMS element. Due to the presence of the isolated well that surrounds the poly-resistor, the substrate resistance does not influence the dynamic behavior of each MEMS element in the MEMS DVC and noise in the RF signal is reduced.

Abstract: Schottky structure fabrication includes forming two trenches in a semiconductor material. The trenches are separated from each other by a mesa. Sidewalls and a bottom surface of the trenches are lined with a dielectric material. A conductive material is disposed in the trenches lining the dielectric material on the sidewalls and the bottom surface. The conductive material on the bottom surface of the trenches is removed so that a first portion of conductive material remains on a first sidewall of each trench, and a second portion of conductive material remains on a second sidewall of each trench. The first and second portions of conductive material are electrically isolated from each other. The space between the first and second portions of the conductive material is filled with a trench filling insulator material and a Schottky contact is formed between the outermost sidewalls of the two trenches.

Abstract: A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. A resulting semiconductor structure is also disclosed.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.