Patents Examined by Shannon Yi
  • Patent number: 9748235
    Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Aritra Dasgupta, Benjamin G. Moser, Mohammad Hasanuzzaman, Murshed M. Chowdhury, Shahrukh A. Khan, Shafaat Ahmed, Joyeeta Nag
  • Patent number: 9726634
    Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 9716089
    Abstract: A semiconductor device includes a plurality of transistor components disposed on a semiconductor substrate, and a guard ring disposed on the semiconductor substrate surrounding the transistor components. The guard ring includes a plurality of fin structures disposed in parallel on the semiconductor substrate, a plurality of first conductive connection members disposed on the fin structures and connecting at least two fin structures, and a plurality of second conductive connection members connecting at least two first conductive connection members. The first conductive connection members and the second conductive connection members are formed as one structure.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: July 25, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Hao Zhong, Yunchu Yu, Yihua Shen
  • Patent number: 9711395
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Patent number: 9711534
    Abstract: A device includes a substrate layer, a diamond layer, and a device layer. The device layer is patterned. The diamond layer is to conform to a pattern associated with the device layer.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: July 18, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Di Liang, Raymond G Beausoleil
  • Patent number: 9700420
    Abstract: Methods and devices for correcting wear pattern defects in joints. The methods and devices described herein allow for the restoration of correcting abnormal biomechanical loading conditions in a joint brought on by wear pattern defects, and also can, in embodiments, permit correction of proper kinematic movement.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 11, 2017
    Assignee: ConforMIS, Inc.
    Inventors: Wolfgang Fitz, Raymond A. Bojarski, Philipp Lang
  • Patent number: 9679897
    Abstract: A nanofluidic structure including a semiconductor substrate and a dielectric layer positioned above and in contact with the semiconductor substrate. A first reservoir and a second reservoir are defined by the semiconductor substrate and the dielectric layer. The second reservoir is spaced apart from the first reservoir. Bottom passage fins protrude from the semiconductor substrate and extend from the first reservoir to the second reservoir. Top passage fins, above and spaced apart from the bottom passage fins, extend from the first reservoir to the second reservoir. Nanofluidic passages between the top and bottom fins connect the first reservoir and the second reservoir. Each of the nanofluidic passages includes a bottom wall, a top wall and sidewalls. The bottom wall is defined by a respective bottom passage fin. The top wall is defined by a respective top passage fin. The sidewalls are defined by the dielectric layer.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9676193
    Abstract: A substrate processing method includes forming a first hole in a first surface of a silicon substrate to have a depth that it does not extend through the substrate and forming a second hole in a second surface to make the second hole to communicate with the first hole, so that a through hole formed of the first and second holes is formed in the substrate. The process of forming the second hole includes forming a communication portion wider than an opening of the first hole between the first and second holes after the second hole has been made to communicate with the first hole by dry etching.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: June 13, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masataka Kato, Hiroshi Higuchi, Yoshinao Ogata, Seiko Minami, Masaya Uyama, Toshiyasu Sakai
  • Patent number: 9675262
    Abstract: The disclosed technology generally relates to sensors comprising a two-dimensional electron gas (2DEG), and more particularly to an AlGaN/GaN 2DEG-based sensor for sensing signals associated with electrocardiograms, and methods of using the same. In one aspect, a sensor comprises a substrate and a GaN/AlGaN hetero-junction structure formed on the substrate and configured to form a two-dimensional electron gas (2DEG) channel within the GaN/AlGaN hetero-junction structure. The sensor additionally comprises Ohmic contacts connected to electrical metallizations and to the 2DEG channel, wherein the GaN/AlGaN hetero-junction structure has a recess formed between the Ohmic contacts. The sensor further comprises a dielectric layer formed on a top surface of the sensor.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: June 13, 2017
    Assignee: Stichting IMEC Nederland
    Inventors: Roman Vitushinsky, Peter Offermans
  • Patent number: 9653608
    Abstract: An array substrate and a manufacturing method thereof, a display device and a thin film transistor are provided. The method includes forming a pattern that includes an active layer, a pixel electrode and a data line on a base substrate; forming a pattern that includes a gate insulating layer and at least two gate via-holes therein, the at least two gate via-holes are located in regions in the gate insulating layer that correspond to outer surroundings of the active layer and do not overlap with areas where the pixel electrode and the data line are located; forming a pattern that includes a gate line and at least two gate electrodes, the at least two gate electrodes are connected to the gate line, and are provided in the at least two gate via-holes, respectively. With this method, the fabricating process and the fabricating cost are saved.
    Type: Grant
    Filed: May 24, 2014
    Date of Patent: May 16, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Seungjin Choi, Heecheol Kim, Youngsuk Song, Seongyeol Yoo
  • Patent number: 9640538
    Abstract: Methods for forming an eDRAM with replacement metal gate technology and the resulting device are disclosed. Embodiments include forming first and second dummy electrodes on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an ILD; removing the first and second dummy electrodes, forming first and second cavities, respectively; forming a hardmask over the substrate, exposing the first cavity; forming a deep trench in the substrate through the first cavity; removing the hardmask; and forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanxiang Liu, Min-hwa Chi
  • Patent number: 9620359
    Abstract: The Siemens process for deposition of polycrystalline silicon in the form of rods in a sealed reactor is improved by, after introduction of deposition gas has ceased, introducing a ventilating gas into the partially sealed reactor, withdrawing a gas stream from the reactor, and monitoring the components in the gas stream withdrawn until a desired concentration of one or more components is reached, and opening the reactor to remove the rods.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: April 11, 2017
    Assignee: Wacker Chemie AG
    Inventors: Barbara Mueller, Thomas Koch
  • Patent number: 9607989
    Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xusheng Wu, Yue Hu, Xin Wang, Yong Meng Lee, Wen-Pin Peng, Lun Zhao, Wei-Hua Tong
  • Patent number: 9590611
    Abstract: Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using structures configured to cooperatively control a common semi-conductive channel region (SCR). One embodiment includes providing a metal oxide semiconductor field effect transistor (MOSFET) section formed with an exemplary SCR and two junction field effect transistor (JFET) gates on opposing sides of the MOSFET's SCR such that operation of the JFET modulates or controls current through the MOSFET's. With two JFET gate terminals to modulate various embodiments' signal(s), an improved mixer, demodulator, and gain control element in, e.g., analog circuits can be realized. Additionally, a direct current (DC)-biased terminal of one embodiment decreases cross-talk with other devices. A lens structure can also be incorporated into MOSFET structures to further adjust operation of the MOSFET.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: March 7, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Patrick L. Cole, Adam R. Duncan
  • Patent number: 9548237
    Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement region. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: January 17, 2017
    Assignee: SOITEC
    Inventors: Gweltaz Gaudin, Oleg Kononchuk, Ionut Radu
  • Patent number: 9536742
    Abstract: The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; and applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure. The method also includes applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region and forming a body region on one side of the drift region in the semiconductor substrate. The method further includes forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 3, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Dae-Sub Jung, Guohao Cao
  • Patent number: 9515181
    Abstract: Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer. The semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate. The exemplary method further comprises applying a treatment to the semiconductor on insulator wafer using the gate as a mask. The treatment creates a treated insulator region in the buried insulator. The exemplary method also comprises removing at least a portion of the substrate. The exemplary method also comprises, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region after removing that portion of the substrate.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: December 6, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Stephen A. Fanelli
  • Patent number: 9502291
    Abstract: A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: November 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kilho Lee, Shinhee Han
  • Patent number: 9457559
    Abstract: A method of making a semiconductor substrate having a through-hole includes a step of forming an etching mask on a semiconductor substrate in accordance with a pattern corresponding to the through-hole, and a step of forming the through-hole by etching the semiconductor substrate, on which the etching mask has been formed, by reactive ion etching. At least a part of the pattern corresponding to the through-hole is formed so that the semiconductor substrate is exposed in a frame-like shape along the inner edge of the through-hole.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: October 4, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Higuchi, Takayuki Kamimura
  • Patent number: 9368512
    Abstract: A semiconductor structure is provided that includes a semiconductor fin extending upwards from a surface of a substrate. A source/drain structure is located on each side of the semiconductor fin. The source/drain structure comprises an upper source/drain portion having a faceted topmost surface and located on an upper portion of the semiconductor fin, and a lower source/drain portion having a faceted topmost surface and located on a lower portion of the semiconductor fin. In accordance with the present application, upper source/drain portion of the source/drain structure is spaced apart from the lower source/drain portion of the source/drain structure by a dielectric spacer portion.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: June 14, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Alexander Reznicek, Dominic J. Schepis, Charan V. V. S. Surisetty