Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device comprises a first fin type active pattern formed on a substrate and extending in a first direction and including first to third parts. At least one dimension of the third part measuring less than the corresponding dimension of the first part. A gate electrode extending in a second direction different from the first direction is at least partially formed on the first part of the fin type active pattern. A first source/drain is formed on the third part of the fin type active pattern.

Abstract: To provide a film which is excellent in releasing property with respect to a resin sealed portion and excellent in low migration property and peeling property with respect to a semiconductor chip, a source electrode or a sealing glass and which is suitable as a mold release film for producing a semiconductor element having a part of the surface of a semiconductor chip, source electrode or sealing glass exposed. A film 1 which comprises a substrate 3 and an adhesive layer 5, wherein the storage elastic modulus at 180° C.

Abstract: A display panel and a manufacturing method therefore, and a display apparatus. The display panel comprises: a first substrate (1); a second substrate (2) arranged and attached opposite the first substrate (1), wherein a sealing adhesive layer (3) is provided between the first substrate (1) and the second substrate (2), and the sealing adhesive layer (3) is configured to bond the first substrate (1) and the second substrate (2) to form a sealed structure; and a fusion layer (4), wherein the fusion layer (4) is provided between the sealing adhesive layer (3) and the first substrate (1), and is located corresponding to the sealing adhesive layer (3); and the fusion layer (4) comprises a metal material.

Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a package substrate. A heat dissipation feature is attached on a first side of the first die. A second die is mounted on a second side of the first die, wherein the second die is at least partially disposed in a through hole formed in the package substrate. An encapsulant is formed on the first side of the package substrate around the first die.

Abstract: The present invention provides an array substrate and a manufacturing method thereof, and a display device. The array substrate of the present invention comprises: common electrodes, pixel electrodes, common electrode lines and at least one auxiliary common electrode line, and the at least one auxiliary common electrode line is arranged to intersect with and be electrically connected to the common electrode lines. The manufacturing method of an array substrate of the present invention comprises a step of forming common electrode lines and a step of forming auxiliary common electrode lines, wherein the auxiliary common electrode lines are arranged to intersect with and be electrically connected to the common electrode lines. The display device of the present invention comprises the above array substrate.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: A complementary tunneling field effect transistor and a manufacturing method are disclosed, which includes: a first drain region and a first source region that are disposed on a substrate, where they include a first dopant; a first channel that is disposed on the first drain region and a second channel that is disposed on the first source region; a second source region that is disposed on the first channel and a second drain region that is disposed on the second channel, where they include a second dopant; a first epitaxial layer that is disposed on the first drain region and the second source region, and a second epitaxial layer that is disposed on the second drain region and the first source region; and a first gate stack layer that is disposed on the first epitaxial layer, and a second gate stack layer that is disposed on the second epitaxial layer.

Abstract: A semiconductor device has an insulating surface provided with a transistor and a capacitor. The transistor includes a gate electrode, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film, and a first conductive film serving as a pair of electrodes in contact with the oxide semiconductor film. An oxide insulating film in contact with the oxide semiconductor film, a metal oxide film over the oxide insulating film, and a second conductive film serving as a pixel electrode which is in an opening in the metal oxide film and is in contact with the first conductive film are provided. The capacitor includes a film having conductivity over the gate insulating film, the second conductive film, and the metal oxide film provided between the film having conductivity and the second conductive film.

Abstract: A semiconductor integrated circuit device, including a semiconductor layer of a first conductivity type, a first well region of a second conductivity type, a second well region of the second conductivity type, and a third well region of the first conductivity type. The device further includes an isolation region electrically isolating a predetermined region in the first well region, a first high-concentration region of the second conductivity type, disposed outside the isolation region and inside one of the first well region and the second well region, and a second high-concentration region of the second conductivity type, disposed inside the isolation region and inside one of the first well region and the second well region. The first and second high-concentration regions each have an impurity concentration that is higher than that of the first well region.

Abstract: A display device including: a plurality of unit portions repeatedly arranged in a first direction and a second direction, wherein the second direction is different from the first direction; a plurality of display units respectively arranged above the plurality of unit portions; and a plurality of encapsulation layers respectively encapsulating the plurality of display units, wherein each of the plurality of unit portions includes an island where a display unit and an encapsulation layer are located, and at least one connection unit connected to the island, and islands of two unit portions adjacent to each other are spaced apart from each other, and connection units of the two unit portions adjacent to each other are connected to each other.

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

Abstract: A MEMS device has a substrate with a structure surface and an opposing exterior surface, microstructure formed on the structure surface of the substrate, and a cap coupled with the substrate to form a hermetically sealed interior chamber containing the microstructure. The substrate forms a trench extending from, and being open to, the opposing exterior surface to produce a sensor region and a second region. Specifically, the second region is radially outward of the sensor region. The MEMS device also has a spring integrally formed at least in part within the trench to mechanically connect the sensor region and the second region, and other structure integral with the substrate. The spring or the other structure at least in part hermetically seal the interior chamber.

Abstract: The present disclosure relates to a MEMs package having a heating element configured to adjust a pressure within a hermetically sealed chamber by inducing out-gassing of into the chamber, and an associated method. In some embodiments, the MEMs package has a CMOS substrate having one or more semiconductor devices arranged within a semiconductor body. A MEMs structure is connected to the CMOS substrate and has a micro-electromechanical (MEMs) device. The CMOS substrate and the MEMs structure form a hermetically sealed chamber abutting the MEMs device. A heating element is electrically coupled to the one or more semiconductor devices and is separated from the hermetically sealed chamber by an out-gassing layer arranged along an interior surface of the hermetically sealed chamber. By operating the heating element to cause the out-gassing layer to release a gas, the pressure of the hermetically sealed chamber can be adjusted after it is formed.

Abstract: A display device and a testing method thereof are disclosed, in which a defect caused by an overflow of an organic film constituting an encapsulation film can be detected. The display device comprises a substrate including a display area where pixels are arranged, and a pad area including a plurality of pads formed outside the display area; an encapsulation film covering the display area, including at least one inorganic film and at least one organic film; a dam arranged between the display area and the pad area; and a conductive testing line arranged between the dam and the pad area and not electrically connected with another conductive line or electrode arranged on the substrate.

Abstract: An organic light emitting display device including a first electrode defined into red, green and blue sub-pixel regions; a hole injection layer disposed on the first electrode; a first hole transport layer disposed on the hole injection layer; first, second and third organic emission layers arranged on the first hole transport layer opposite to the respective red, green and blue sub-pixel regions; an electron transport layer disposed on the first, second and third organic emission layers; and a second electrode disposed on the electron transport layer. The second organic emission layer opposite to the green sub-pixel region is formed in a stacked structure including first and second hole host layers and a dopant host layer.

Abstract: According to an embodiment, a micro-fabricated test structure includes a structure mechanically coupled between two rigid anchors and disposed above a substrate. The structure is released from the substrate and includes a test layer mechanically coupled between the two rigid anchors. The test layer includes a first region having a first cross-sectional area and a constricted region having a second cross-sectional area smaller than the first cross-sectional area. The structure also includes a first tensile stressed layer disposed on a surface of the test layer adjacent the first region.

Abstract: An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

Abstract: A light field imaging device includes an image sensor having a plurality of pixels arranged two-dimensionally therein; a microlens array formed over the image sensor, the microlens array having a plurality of microlenses arranged two-dimensionally therein; and a plurality of support structures formed between the image sensor and the microlens array for providing an air gap therebetween.

Abstract: An electronic device can comprise a first electronic module; a second electronic module; and a hermetic electric interconnect to hermetically couple them. The hermetic electric interconnect can comprise a bottom metal layer; a bottom insulating layer, deposited on the bottom metal layer to insulate the bottom metal layer; an interconnect metal layer, deposited on the bottom insulating layer, and deposited to form a bottom sealing ring; and patterned to form electrical connections between contact pads, and to form a middle sealing ring; a patterned top insulating layer, deposited on the interconnect metal layer to insulate the interconnect metal layer; and patterned to form feedthrough holes; and a top metal layer, deposited on the top insulating layer to start forming contacts by filling the feedthrough holes; and patterned to complete forming contacts through the feedthrough holes, to form a separate barrier layer, and to complete forming the top sealing ring.