Abstract: An IGBT region includes a collector layer, a first drift layer, a first body layer, an emitter layer, and a trench gate reaching the first drift layer through the first body layer from a front surface side of a semiconductor substrate. A diode region includes a cathode layer, a second drift layer, and a second body layer. A lifetime control region which includes a peak of a crystal defect density is provided in the first drift layer and the second drift layer that are located between a depth of a lower end of the trench gate and surfaces of the first drift layer and the second drift layer. A silicon nitride film is further provided above the trench gate on the front surface side of the semiconductor substrate.

Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

Abstract: A semiconductor device includes: a substrate on which a first contact portion is formed; a lower shield plate provided above the substrate to avoid the first contact portion and including a magnetic substance; a semiconductor chip provided above the lower shield plate and including a second contact portion electrically connected to the first contact portion, and a connection member that electrically connects the first contact portion and the second contact portion; and an upper shield plate provided above the semiconductor chip to avoid the second contact portion and the connection member and including a magnetic substance. An end of at least one of the lower shield plate and the upper shield plate is bent toward the other one of the lower shield plate and the upper shield plate so have a side wall portion whose tip is connected to the other one of the lower shield plate and the upper shield plate.

Abstract: To provide an electroconductive thin film, containing: a metal oxide containing indium and tin; and gold.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: A radiation detector is provided including a cathode, an anode, and a semiconductor wafer. The semiconductor wafer has opposed first and second surfaces. The cathode is mounted to the first surface, and the anode is mounted to the second surface. The semiconductor wafer is configured to be biased by a voltage between the cathode and the anode to generate an electrical field in the semiconductor wafer and to generate electrical signals responsive to absorbed radiation. The electrical field has an intensity having at least one local maximum disposed proximate to a corresponding at least one of the first surface or second surface.

Abstract: The present disclosure relates to a flexible organic light emitting diode display having an edge bending structure. The organic light emitting diode display according to an embodiment includes a flexible plate including a display area, a non-display area surrounding the display area, and an edge bending area near the display area in the non-display area; a first line disposed in the non-display area on the flexible plate; a first buffer layer covering the first line; a second line on the first buffer layer in the non-display area; a second buffer layer covering the second line; gate elements disposed on the second buffer layer; an intermediate insulating layer covering the gate elements; data elements, and a connecting electrode connecting the first line to the second line on the intermediate insulating layer; and a plurality of trenches disposed at the edge bending area and penetrating the intermediate insulating layer, the second buffer layer and the first buffer layer.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: fainting a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.

Abstract: A solar cell employing nanocrystalline superlattice material and amorphous structure and method of constructing the same provides improved efficiency when converting sunlight to power. The photovoltaic (PV) solar cell includes an intrinsic superlattice material deposited between the p-doped layer and the n-doped layer. The superlattice material is comprised of a plurality of sublayers which effectively create a graded band gap and multi-band gap for the superlattice material. The sublayers can include a nanocrystalline Si:H layer, an amorphous SiGe:H layer and an amorphous SiC:H layer. Varying the thickness of each layer results in an effective energy gap that is graded as desired for improved efficiency. Methods of constructing single junction and parallel configured two junction solar cells include depositing the various layers on a substrate such as stainless steel or glass.

Abstract: A sensor device for remote monitoring of a waste container, the sensor device including one or more sensors for sensing an amount of waste and an environment within the waste container, a data processing unit for processing sensor signals indicative of the amount of waste and the environment within the waste container, a communication interface for enabling the sensor device to communicate information corresponding to the sensor signals to a remote location. The sensor device is mounted to an upper lid of the waste container in a spaced apart manner by placing one or more spacing elements and a heat reflecting layer arranged between the sensor device and the upper lid to provide a thermal barrier between an underside surface of the waste container lid and the sensor device.

Abstract: A method of fabricating a display device including forming one or more thin-film transistors (“TFTs”) each configured to include an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate. A storage capacitor including a first storage electrode and a second storage electrode overlapping the first storage electrode with the gate insulating layer interposed there between is also formed on the substrate. A top surface of the first storage electrode may include hillocks and the gate insulating layer is formed between the first storage electrode and the second storage electrode to conform to the shape of the top surface of the first storage electrode with the hillocks.

Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

Abstract: A power circuit is described that includes a semiconductor body having a common substrate and a Gallium Nitride (GaN) based substrate. The GaN based substrate includes one or more GaN devices adjacent to a front side of the common substrate. The common substrate is electrically coupled to a node of the power circuit. The node of the power circuit is at a particular potential that is equal to, or more negative than, a potential at one or more load terminals of the one or more GaN devices.

Abstract: The present invention discloses a nitroxide fluorescent powder comprising an inorganic compound containing M, A, B, O, N, and R elements; in which the M element is at least one of Ca, Sr, Ba, Mg, Li, Na, and K, the A element is at least one of B, Al, Ga, and In, the B element is at least one of C, Si, Ge, and Sn, the R element is at least one of Ce, Eu, Lu, Dy, Gd, and Ho, characterized in that the inorganic compound forms a crystal in a crystalline phase, and the oxygen atom content in the crystal in a crystalline phase is in an increasing structural distribution from a core to surface of the crystal. The nitroxide fluorescent powder and the nitroxide illuminant of the present invention have the advantages of good chemical stability, good aging and light decay resistance, and high luminescent efficiency, and are useful for various luminescent devices. The preparation method of the present invention is easy and reliable and useful for industrial mass production.

Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Abstract: A semiconductor device and a method for fabricating the device. The method includes: forming a STI in a substrate having a nFET and a pFET region; depositing a high-k layer and a TiN layer; depositing a polycrystalline silicon layer; forming a block level litho layer; removing a portion of the polycrystalline silicon layer; removing the block level litho layer; forming a first protective layer; depositing a fill layer above the pFET region; removing the first protective layer; cutting the TiN layer and the high-k layer to expose a portion of the STI; depositing a second protective layer on the STI; removing the fill layer; removing the TiN layer above the pFET region; treating the high-k layer with a work function tuning process; removing the polycrystalline silicon layer and TiN layer; and depositing a metal layer on the high-k layer and the second protective layer.

Abstract: A semiconductor structure includes a substrate, a buffer layer, and a two-dimensional layered material. The buffer layer is above the substrate and is formed from one of SiC and a nitride-based material. The two-dimensional layered material is above the buffer material. The construction as such permits formation, e.g., of a channel of a transistor from the two-dimensional layered material.

Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.