Abstract: A production method for a thermoelectric conversion module having a thermoelectric conversion element and an electrode, which are metallurgically bonded together via a porous metal layer. The porous metal layer is made of nickel or silver and has a density ratio of 50 to 90%.

Abstract: An integrated diode array and a corresponding manufacturing method are provided. The integrated diode array includes a substrate having an upper side, and a plurality of blocks of several diodes, which are positioned in a planar manner and are suspended at the substrate above a cavity situated below them in the substrate. The blocks are separated from one another by respective gaps, and within a specific block, the individual diodes are electrically insulated from one another by first STI trenches situated between them.

Abstract: Embodiments of an image sensor are provided. The image sensor includes a sensing layer, a filter unit and a microlens. The filter unit is disposed on the sensing layer, and the microlens is disposed on the filter unit. The filter unit has a gradient refractive index. Therefore, the sensitivity of the image sensor is improved.

Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Abstract: A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n+ emitter region and an n? drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.

Abstract: One disclosed embodiment comprises formation of a padless via in a substrate. The padless via includes a hole through a metal layer blanketing the substrate, as well as the underlying substrate. An inner wall of the padless via hole receives a seed layer of a conductive material. Electrolytic differential plating is then performed, resulting in a preferential accumulation of a conductive plating material on the via inner wall, relative to that deposited on a surface of the substrate. In one embodiment, the differential plating is performed by addition of an organic suppressant to a plating bath.

Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an interlayer insulating film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Abstract: A stacked semiconductor device includes a first pair of vertically stacked self-aligned nanowires, a second pair of vertically stacked self-aligned nanowires, and a gate upon a semiconductor substrate, the gate surrounding portions of the first pair of vertically stacked self-aligned nanowires and the second pair of vertically stacked self-aligned nanowires. First epitaxy may merge the first pair of vertically stacked self-aligned nanowires and second epitaxy may merge second pair of vertically stacked self-aligned nanowires. The stacked semiconductor device may be fabricated by forming a lattice-fin upon the semiconductor substrate and the gate surrounding a portion of the lattice-fin. The vertically stacked self-aligned nanowires may be formed by selectively removing a plurality of layers from the lattice-fin.

Abstract: A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Abstract: A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A non-magnetic heating structure is formed of a barrier seed layer disposed on a buffer layer. A non-magnetic tunnel barrier is disposed on the barrier seed layer. A barrier cap layer is disposed on the non-magnetic tunnel barrier. A top buffer layer is disposed on the barrier cap layer. An antiferromagnetic layer is disposed on the top buffer layer of the non-magnetic heating structure. A magnetic tunnel junction is disposed on the antiferromagnetic layer. The magnetic tunnel junction includes a ferromagnetic storage layer disposed on the antiferromagnetic layer, a non-magnetic active tunnel barrier disposed on the ferromagnetic storage layer, and a ferromagnetic sense layer disposed on the non-magnetic active tunnel barrier.

Abstract: Provided herein is a bump including a diffusion barrier bi-layer, the bump having: a conductive layer; a first diffusion barrier layer formed on or above the conductive layer, and comprising an alloy of nickel and phosphorus; a second diffusion barrier formed on or above the first diffusion barrier layer, and comprising copper; and a solder layer formed on or above the second diffusion barrier layer. A manufacturing method for producing a bump is also provided.

Abstract: A semiconductor device includes a semiconductor die having an outer edge and an active area defining a main horizontal surface and being spaced apart from the outer edge. The semiconductor device further includes an edge termination structure having a closed vertical trench surrounding the active area. The edge termination structure further includes at least one vertical trench arranged, in a horizontal cross-section, between the closed vertical trench and the active area. The at least one vertical trench includes an insulated side wall forming an acute angle with the outer edge.

Abstract: A packaged MEMS device and a method of calibrating a packaged MEMS device are disclosed. In one embodiment a packaged MEMS device comprises a carrier, a MEMS device disposed on the substrate, a signal processing device disposed on the carrier, a validation circuit disposed on the carrier; and an encapsulation disposed on the carrier, wherein the encapsulation encapsulates the MEMS device, the signal processing device and the memory element.

Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.

Abstract: A liquid crystal display device having a touch sensor embedded therein is disclosed. The present invention includes a liquid crystal layer between first and second substrates, a pixel on the second substrate to apply a horizontal electric field to the liquid crystal layer, a touch sensor on the second substrate, the touch sensor detecting a touch by forming a touch capacitor with a touch object for touching the first substrate, and a readout line outputting a sensing signal from the touch sensor. The touch sensor includes a sensing electrode on the second substrate to form the sensing capacitor with the touch object, first and second sensor gate lines, a first sensor thin film transistor supplying a sensing driving voltage to the sensing electrode in response to a control of the first sensor gate line, and a second sensor thin film transistor supplying electric charges of the sensing electrode as the sensing signal in response to a control of the second sensor gate line.

Abstract: The organic electroluminescent element has a transparent substrate, a transparent first electrode, an organic layer, a second electrode, and a light-outcoupling layer. The light-outcoupling layer is formed between the transparent substrate and the first electrode. The first electrode, the organic layer and the second electrode constitute an electroluminescent laminate. A covering substrate facing the transparent substrate is adhered to the surface of the transparent substrate via an adhesive sealing portion surrounding the periphery of the electroluminescent laminate. A connection electrode extending outward from inside a surrounded region where the electroluminescent laminate is covered with the covering substrate is formed at least on the surface of the light-outcoupling layer. The average thickness of the light-outcoupling layer in an adhesion region where the adhesive sealing portion is formed is smaller than the thickness in the central region where the electroluminescent laminate is formed.

Abstract: The invention provides a thin-film transistor substrate, including: a substrate; a metal lead structure formed on the substrate, wherein the metal lead structure includes: a main conductor layer formed on the substrate, wherein the main conductor has a sidewall; a top conductor layer having a first portion, second portion and third portion, wherein the first portion is formed on the main conductor layer, the second portion is formed on the sidewall of the main conductor layer, and the third portion is formed on the substrate, and a continuous structure is formed by the first portion, the second portion and the third portion.

Abstract: A semiconductor device, having an electrode pad as a part of wirings on the uppermost layer thereof, includes a passivation film and a bump electrode for external connection. The passivation film is formed on the electrode pad, and the bump electrode is formed on the passivation film and electrically connected to the electrode pad. The electrode pad is formed so as to be smaller in size than the bump electrode, and parts of the wiring on the uppermost layer are formed under the bump electrode. In this manner, it is possible to utilize the area under the bump electrode effectively without sacrificing flatness of the passivation film. As a result, the semiconductor device and the semiconductor package can be made smaller.

Abstract: The present invention relates to insertion of a substrate separation step in fabrication of electronics, optoelectronics and microelectromechanical devices (MEMS), particularly double-sided devices which functionalities require designs and fabrication processes at both sides of substrates. In the method, both sides of a semiconductor substrate are processed, prior to slicing of the substrate from the sidewall into two pieces, and the device fabrication continues on the new surfaces of the two resulting substrates after the slicing. The present invention is applicable to various schemes in crystalline silicon solar cell fabrication. Compared with the baseline manufacturing flow, the method can produce two solar cells from one starting substrate, with a potentially significant reduction in production cost per final solar cell.