Abstract: A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: There are provided a display panel, a display unit, and an electronic apparatus that make it possible to reduce a leakage current arising between adjacent pixels. The display panel includes a plurality of pixels at a display region. Each of the pixels has an organic EL device, and a pixel circuit that drives the organic EL device. The organic EL device has an anode electrode, a cathode electrode, and an organic layer that is provided between the anode electrode and the cathode electrode. A side surface of the anode electrode is structured in such a manner that the cross-sectional area of the anode electrode on the side of the cathode electrode is larger than that of the anode electrode on the opposite side of the cathode electrode.

Abstract: A semiconductor device and a method for fabricating the device. The method includes: forming a STI in a substrate having a nFET and a pFET region; depositing a high-k layer and a TiN layer; depositing a polycrystalline silicon layer; forming a block level litho layer; removing a portion of the polycrystalline silicon layer; removing the block level litho layer; forming a first protective layer; depositing a fill layer above the pFET region; removing the first protective layer; cutting the TiN layer and the high-k layer to expose a portion of the STI; depositing a second protective layer on the STI; removing the fill layer; removing the TiN layer above the pFET region; treating the high-k layer with a work function tuning process; removing the polycrystalline silicon layer and TiN layer; and depositing a metal layer on the high-k layer and the second protective layer.

Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.

Abstract: A semiconductor device includes an n-type semiconductor substrate, which has a main surface having an element region and an outer peripheral region surrounding the element region; a p-type guard ring, which includes: a lowly-doped p-type region disposed on an upper surface of the semiconductor substrate in the outer peripheral region surrounding the element region; and a highly-doped p-type region disposed on an inner side of the lowly-doped p-type region and having an impurity concentration higher than an impurity concentration of the lowly-doped p-type region, wherein a side surface and a bottom surface of the highly-doped p-type region are covered by the lowly-doped p-type region such that the highly-doped p-type region is not in contact with the n-type region; and an ohmic junction electrode, which forms an ohmic junction with the highly-doped p-type region.

Abstract: Methods of preparing layouts for semiconductor devices and semiconductor devices fabricated using the layouts are provided. Preparing the layouts for semiconductor devices may include disposing assistant patterns near a main gate pattern that is provided on a weak active pattern. The weak active pattern may be, for example, an outermost one of active patterns and may be one expected to have an increased width during a fabrication process.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: A method is provided of forming an interconnect structure. The method comprises forming a first dielectric layer overlying a first conductive layer, etching a trench opening in the first dielectric layer, depositing a sacrificial material layer in the trench opening, and forming a second conductive layer overlying the sacrificial layer. The method also comprises forming a via to the sacrificial layer, and performing an etch to remove the sacrificial material layer through the via and leave a resultant air gap between the first conductive layer and the second conductive layer decreasing the effective dielectric constant between the first and second conductive layers.

Abstract: A thin film transistor array panel according to an exemplary embodiment includes: a substrate; a thin film transistor positioned on the substrate; a first electrode connected to the thin film transistor; and a diffractive layer positioned between the substrate and the thin film transistor. The diffractive layer is positioned within a boundary line of semiconductors of the thin film transistor.

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract: Methods for fabricating a piezoelectric device are provided. The methods can include providing a substrate and forming a nanocrystalline diamond layer on a first surface of the substrate. The methods can also include depositing a piezoelectric layer on a first surface of the nanocrystalline diamond layer.

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

Abstract: An organic electroluminescent device that includes at least two phosphorescent emitting layers, where phosphorescent emitter layer 1 comprises a hole-conducting matrix material and two different phosphorescent emitters, and phosphorescent emitter layer 2 comprises an electron-conducting matrix material and a phosphorescent emitter.

Abstract: Disclosed is a semiconductor structure comprising a single crystal substrate, a channel layer formed above the substrate from a transition metal dichalcogenides (TMDC) material, and a single crystal epitaxial buffer layer formed between the substrate and the channel layer, wherein the buffer layer is formed from material having a lattice constant mismatch of less than 5% with the lattice constant of the channel layer material. Also, disclosed is a method of forming a semiconductor structure comprising selecting a substrate formed from a single crystal material, preparing the substrate for template growth, growing a template on the substrate wherein the template is formed from single crystal material, and growing channel material on the template wherein the channel material is formed from a TMDC material and wherein the buffer layer material has a lattice constant mismatch of less than 5% with the lattice constant of the channel layer material.

Abstract: A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and concurrently forming a stripe-shaped mask layer on the substrate; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, and the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.

Abstract: An organic light-emitting diode display can include an improved aperture ratio by configuring a circuit pattern between neighboring subpixels in a symmetrical fashion such that the subpixels share signal lines. Each pixel of the organic light-emitting diode display is formed in a symmetrical fashion with respect to one contact area, the number of reference connecting patterns can be reduced and therefore the area occupied by an opening area for each pixel can be made wider, thus leading to an improved aperture ratio.

Abstract: The invention relates to transferring, in one exposure, a single-mask feature to form two features on an underlying material. Specifically, a doubled walled structure (i.e. a center opening flanked by adjacent openings) is formed. Advantageously, the openings may be sub-resolution openings. The center opening may be a line flanked by two other lines. The center opening may be circular and surrounded by an outer ring, thus forming a double wall ring structure. In an electronic fuse embodiment, the double wall ring structure is a via filled with a conductor that contacts a lower and upper level metal. In deep trench embodiment, the double wall ring structure is a deep trench in a semiconductor substrate filled with insulating material. In such a way the surface area of the trench is increased thereby increasing capacitance.

Abstract: An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.

Abstract: A method of attaching bond wires to bond pads on an active surface of a semiconductor die, where the bond pads are disposed along four side edges of the die, and have aluminum top layers. The method includes attaching first bond wires to first bond pads on first and second opposing sides of the die using a first group of settings and attaching second bond wires to the bond pads on third and fourth sides of the die that oppose each other and are adjacent the first and second sides, using a second group of settings. The first and second groups of settings include first and second scrub settings that are different from each other. Employing two separate scrub settings allows for reduced splashing of the aluminum cap layer on the die pad from splashing onto passivation edges of the bond pads.