Patents Examined by Shawn Eland
  • Patent number: 7721062
    Abstract: A system and method for detecting buffer leaks in a files system utilizing consistency points is provided. Upon receipt of a write operation, a buffer check control structure is written to a raw data buffer. The buffer check control structure comprises a set of magic numbers and a consistency point counter identifying the current CP. At write allocation time, the buffer check control structure is examined to determine that the buffer is being committed to disk during the correct CP.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: May 18, 2010
    Assignee: NetApp, Inc.
    Inventors: Robert L. Fair, Eric Hamilton
  • Patent number: 7716439
    Abstract: A data processing system includes a readout unit, a device ID storage unit, a storage medium writing unit, a determination unit, and a processing unit. The readout unit reads out data that have been stored on a storage medium, where the storage medium is removably mounted in an external storage unit. The device ID storage unit stores a device ID that is peculiar to a device. The storage medium writing unit writes the device ID that has been stored in the device ID storage unit to the storage medium. The determination unit makes a determination as to whether the device ID that has been written to the storage medium and the device ID that has been stored in the device ID storage unit are in agreement. The processing unit carries out either first processing or second processing depending on a determination made by the determination unit.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: May 11, 2010
    Assignee: Roland Corporation
    Inventor: Masayuki Saitoh
  • Patent number: 7702851
    Abstract: The present invention transfers replication logical volumes between and among storage control units in a storage system comprising a plurality of storage control units. To transfer replication logical volumes from a storage control unit to a storage control unit, a virtualization device sets a path to the storage control unit. The storage control unit then prepares a differential bitmap in order to receive access requests. When the preparation is completed, the virtualization device makes access requests to the storage control unit. The storage control unit then hands over the access requests to the storage control unit. Subsequently, the storage control unit performs a process so that the access requests are reflected in a disk device and performs an emergency destage of storing data in a cache memory into disk device. When the emergency destage is ended, the storage control unit connects to an external storage control unit and hands over access requests to the external storage control unit.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: April 20, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Ai Satoyama, Yoshiaki Eguchi, Yasutomo Yamamoto
  • Patent number: 7685391
    Abstract: Kernel and user stack data is stored in relocatable memory. A kernel thread or a user thread can move its own stack data by creating a relocation request and adding the relocation request to a queue of a dedicated thread. The dedicated thread performs the relocation on behalf of the requesting kernel or user thread.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: March 23, 2010
    Assignee: Sun Microsystems, Inc.
    Inventors: Udayakumar Cholleti, Viswanath Knishnamurthy, Stan J. Studzinski
  • Patent number: 7653800
    Abstract: A method for continuous data protection in a storage system, including receiving a first write command to write first data to a partition of a logical volume and then generating a first partition descriptor record (PDR) having a first timestamp. The method further includes storing the first data at a first location, associating the first PDR with the first location, and receiving a second write command, subsequent to the first command, to update the first data with second data. Responsively to the second command, a second PDR having a second timestamp is generated. The second data is stored at a second location, and the second PDR is associated with the second location. The method includes generating a pointer between the first PDR and the second PDR, and accessing the first PDR using the pointer in response to a read command indicating a time prior to the second timestamp.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: January 26, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ofir Zohar, Yaron Revah, Haim Helman, Dror Cohen, Shemer Schwartz
  • Patent number: 7653802
    Abstract: A computing environment maintains the integrity of data stored in system memory. The system has a memory management unit that maintains a plurality of real page numbers. The system also comprises an address bus in communication with the memory management unit. The address bus comprises a plurality of address lines, wherein a value of at least one address line is set by a real page number from the memory management unit. The system has an operating system that controls memory usage by controlling the real page numbers stored in said page table that is accessed by the memory management unit. At least one security feature such as data encryption is selectively applied to data stored in a page of said memory as enabled by a value of said address line set by said real page number.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 26, 2010
    Assignee: Microsoft Corporation
    Inventors: Dinarte R. Morais, Jeffrey A. Andrews
  • Patent number: 7640404
    Abstract: File system write filters are provided which can selectively permit or prevent data from being written-protected storage media. The write filter utilized volatile cache memory to store data that is requested to be written to storage media by applications programming interface function calls. In one aspect, if the particular data is requested to be written to a file that is a file identified on the file exclusion list, the data can be written to the file in non-volatile storage. Otherwise, the particular data is written to volatile cache memory. In another aspect, the write filters can be utilized on computing devices to create a stateless computing device wherein data is written to volatile cache memory in response to write function calls. Upon rebooting, any data that was saved to the volatile cache memory is discarded and the computing device is restored to its original state.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: December 29, 2009
    Assignee: Microsoft Corporation
    Inventors: John F. Macintyre, Saad Syed, Zhong Deng
  • Patent number: 7590797
    Abstract: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: September 15, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Jeffery W. Janzen
  • Patent number: 7587572
    Abstract: A method for managing a computer system process memory allocated to execution of a process configured to use data stored to storage is provided. The process memory has a predetermined size and is filled by uncompressed pages of data necessary to execute the process being copied from the storage. The process memory is partitioned into an uncompressed region having an adjustable first size and a compressed region having an adjustable second size. The uncompressed region includes uncompressed pages of data and the compressed region includes compressed pages of data. The first size of the uncompressed region and the second size of the compressed region are adjusted when a requested page of data necessary for continuing the execution of the process resides in either the storage or the compressed region.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: September 8, 2009
    Assignee: Sun Microsystems, Inc.
    Inventor: Per O. Stenstrom
  • Patent number: 7587563
    Abstract: A writeable clone of a read-only dataset, e.g., an RPPI of a file system, a mirror file system, etc., is created to make the read-only dataset appear from a client's perspective to be modifiable/writeable, yet without actually modifying the read-only dataset itself. Any change attempted to be made on the read-only dataset is stored in the writeable clone. In one embodiment, the clone shares data blocks with the read-only dataset.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: September 8, 2009
    Assignee: Network Appliance, Inc.
    Inventors: Boris Teterin, Manish Dhirajlal Patel
  • Patent number: 7552301
    Abstract: An information processing apparatus is provided which includes a processor for carrying out a pipeline processing over an instruction, a memory provided in the processor and input/output control means for giving access to the memory with a high priority, a memory access arranging method includes a step of causing a clock to be supplied to the processor to wait when a contention of access of the processor and the input/output control means to the memory is generated, a step of executing the access of the input/output control means to the memory, and a step of canceling the clock wait of the processor after ending the access of the input/output control means to the memory, and executing the access of the processor to the memory.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: June 23, 2009
    Assignee: Panasonic Corporation
    Inventor: Atsuhiro Mori
  • Patent number: 7546423
    Abstract: A signal processing system control method and apparatus are described. Various embodiments include a signal processing system with multiple subsystems. A method for controlling the signal processing system includes storing channel records in a designated area of shared memory. Channel records include channel data that include one of multiple discrete signals to be processed by multiple subsystems in a time-multiplexed manner. The channel record includes information used by the multiple subsystems to process a channel, including information used to configure the multiple subsystems, information used to allocate the shared memory, and information used to communicate between multiple subsystems.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: June 9, 2009
    Assignee: SiRF Technology, Inc.
    Inventors: Paul A. Underbrink, Henry Falk
  • Patent number: 7529885
    Abstract: The present invention provides a technique of controlling cache operation on a node device in a computer system that enables transmission and receipt of data between clients and a storage device via the node device. In accordance with a first control method, the data stored in the storage device includes attribute data, as to whether or not the data is cacheable. This application enables the node device to relay non-cacheable data without process of the cache. In accordance with a second control method, the node device encrypts the data when caching the data in the disk. In accordance with a third control method, non-cacheable data is transmitted and received directly without going through the node device. These applications enable the cache in the node device to be restricted, and thereby ensure security.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 5, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Kimura, Satoshi Oshima, Hisashi Hashimoto
  • Patent number: 7506127
    Abstract: A storage system includes a plurality of mass storage devices and a first storage server head to access the mass storage devices in response to client requests, wherein the first storage server head has ownership of the plurality of mass storage devices. Ownership of at least one of the mass storage devices is reassigned to a second storage server head independently of how the second storage server head is connected to the plurality of mass storage devices.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: March 17, 2009
    Assignee: Network Appliance, Inc.
    Inventors: Brad A. Reger, Susan M. Coatney
  • Patent number: 7496725
    Abstract: The invention relates to methods of snapshot operation for a data storage system with a host communicating with a cache memory, a source Virtual Logical Unit Number (VLUN) and a target VLUN, including generating first metadata (e.g., bitmaps and log files pointers) to locate first snapshot data and to indicate when the first snapshot data is in the target VLUN and generating second metadata to locate second snapshot data and to indicate when the second snapshot data is in the target VLUN, wherein the first and second metadata locate the same data in the target VLUN. The invention relates to systems that implement the methods. It relates to destaging data to maintain data consistency including reading metadata for snapshots, searching the metadata to identify snapshots that require original data to be destaged, destaging the original data to target storage, and updating metadata to locate original data and indicate destage completion.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: February 24, 2009
    Assignee: Pillar Data Systems, Inc.
    Inventors: David Alan Burton, Noel Simen Otterness
  • Patent number: 7487296
    Abstract: A multi-stride prefetcher includes a recurring prefetch table that in turn includes a stream table and an index table. The stream table includes a valid field and a tag field. The stream table also includes a thread number field to help support multi-threaded processor cores. The tag field stores a tag from an address associated with a cache miss. The index table includes fields for storing information characterizing a state machine. The fields include a learning bit. The multi-stride prefetcher prefetches data into a cache for a plurality of streams of cache misses, each stream having a plurality of strides.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: February 3, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Sorin Iacobovici, Sudarshan Kadambi, Yuan C. Chou
  • Patent number: 7480761
    Abstract: A system is provided for reading and writing sectors which may be realized as either a disk device to the local operating system, or as a virtual disk device to a virtual machine. A user's computing environment is stored in the network in the form of a disk image, which may be a virtual disk image, for example. The virtual disk is realized on host computers through host-resident virtual machine monitors such as MICROSOFT VIRTUAL PC®. Portable memory devices, such as flash devices, buffer virtual disk writes and cache reads, greatly reducing the performance degradation associated with remote disk access. The cache is mobile so that it can be travel with the user. The flash device remembers commonly used virtual disk content fingerprints so that the host machine's local disk can be used to satisfy many common disk reads when ubiquitous static content is involved. Standard, frequently used software images might be distributed in advance to host machines.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: January 20, 2009
    Assignee: Microsoft Corporation
    Inventors: Andrew Birrell, Edward P. Wobber, Muthukaruppan Annamalai, Ulfar Erlingsson
  • Patent number: 7480766
    Abstract: A re-programmable non-volatile semiconductor memory, such as flash memory, operates to store files with logical addresses including a unique file identifier and offsets of data within the file, termed direct data file storage. Data files generated by a host may be stored directly in such a memory through a file interface. But if a traditional host/memory interface using a continuous logical address space is being used to identify multiple files, the address space is divided into contiguous logical files, and then these files are treated in the same manner as files obtained directly from a host. Both types of interfaces may be included in the same memory system.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: January 20, 2009
    Assignee: Sandisk Corporation
    Inventor: Sergey Anatolievich Gorobets
  • Patent number: 7467270
    Abstract: When there is access to a non-contact type IC, the access is controlled, and external access is notified. A control unit of a non-contact type IC detects access from an external apparatus in response to variation in a load of an antenna, and notifies the detection as access information to a signal judging unit. The signal judging unit refers to history information recorded in a storing unit on the basis of the notified access information, determines whether or not to permit the external apparatus the access, and then notifies a result of the determination to a CPU. On the basis of the notified result of the determination, the CPU controls a display unit, a speaker, a light generating unit, or a vibration generating unit to generate a predetermined stimulus in order to notify the external access. The present invention is applicable to transmission apparatus including a non-contact type IC.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: December 16, 2008
    Assignee: Sony Ericsson Mobile Communications Japan, Inc.
    Inventor: Tomohisa Higuchi
  • Patent number: 7464229
    Abstract: A serial-write, random-access read, memory addresses applications where the data in the memory may change more frequently than would make a PROM suitable, but that changes much less frequently than would require a RAM. This enables the circuit designer to optimize the memory for fast reads, and enables reads to be pipelined. One embodiment of the present invention provides a system that facilitates a serial-write, random-access read, memory. The system includes a plurality of memory cells and a serial access mechanism for writing data into the plurality of memory cells. The system also includes a parallel random-access mechanism for reading data from the plurality of memory cells.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: December 9, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Ian W. Jones