Abstract: A system, apparatus, and method are disclosed for storing predictions as well as examining and using one or more caches for anticipating accesses to a memory. In one embodiment, an exemplary apparatus is a prefetcher for managing predictive accesses with a memory. The prefetcher can include a speculator to generate a range of predictions, and multiple caches. For example, the prefetcher can include a first cache and a second cache to store predictions. An entry of the first cache is addressable by a first representation of an address from the range of predictions, whereas an entry of the second cache is addressable by a second representation of the address. The first and the second representations are compared in parallel against the stored predictions of either the first cache and the second cache, or both.

Abstract: Methods and apparatus are provided for controlling writing and reading of data in an array of A storage fields of a probe-based data storage device in which data is written to and read from the array of storage fields by a corresponding array of probes. One method uses the concept of sub-arrays to provide variable-rate read/write operation. Input data blocks are received for writing to the A-field array, each input data block being writable in A/k0 storage fields where k0 is an integer ?2. For successive groups of k0 blocks, the k0 blocks are written to respective sub-arrays, each of A/k0 storage fields, of the storage field array by selectively writing at one of a series of rates, ranging from 1 block at a time to k0 blocks at a time, in dependence on a desired data write-rate. The blocks can also be read from the sub-arrays by selectively reading at one of a series of rates, ranging from 1 sub-array at a time to k0 sub-arrays at a time, in dependence on a desired data read-rate.

Abstract: A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices is disclosed. The memory devices include a first memory bank configured for data being written to the first memory bank while data is read from the first memory bank at a timeslot and a second memory bank, which is smaller than the first memory bank and configured for writing the data read from the first memory bank to the second memory bank and reading data from the second memory bank. The system further includes an address comparer configured to compare a write address of the first memory bank with a read address of the first memory bank and select data for output from the first memory bank if the write address is smaller than the read address and select data from the second memory bank if the read address is equal to or smaller than the write address.

Abstract: A nonvolatile memory and a data rewriting method of the nonvolatile memory that can readily detect a state of operation at a time of a system failure due to a power failure or the like and quickly and reliably restore the nonvolatile memory to a normal storage state by a simple method. In the nonvolatile memory including a physical block as a storage unit, the physical block having a data area (1) and a redundant area (2), the redundant area (2) includes: a logical block address storing area (3) for storing an address of a corresponding logical block; a previously used physical block address storing area (4) for storing an address of a physical block to be erased; and a status information storing area (6) for storing status information for distinguishing a state of operation in each stage occurring in performing data rewriting operation on the physical block.