Abstract: When a write-back request for writing back new data in a cache memory to disk devices forming a redundant configuration of RAID is generated, a write-back processing unit, reserves a parity buffer area in the cache memory, generates new parity, and then, writes the new data and the new parity to the corresponding disk devices. When an error in which the consistency of RAID is broken occurs in a plurality of the disk devices upon write performed by the write-back processing unit, a recovery processing unit reserves, in the cache memory, a cache stripe area storing data of the entire stripe including the new data which is to be written back, and causes the cache control unit to manage it.

Abstract: Cluster storage collection-based data management is described. In one aspect, and in a distributed system for storing data across a network to multiple data storage nodes, a bounded bandwidth available for data repair in the distributed system is determined. A specific number of stripes are then created on each data storage node of the multiple data storage nodes. The stripes are for placement and replication of data objects across respective ones of the data storage nodes. The specific number of stripes created on each data storage node is a function of the determined bounded data repair bandwidth.

Abstract: The first storage subsystem, when new data is written in a first memory device beyond a certain timing, writes pre-updated data prior to update by said new data into a pre-updated data memory region and, in addition, updates snapshot management information that expresses a snapshot of a data group within the first memory device to information that expresses the snapshot at the certain timing and, at a later timing than the certain timing, judges, on the basis of the snapshot management information, in which of either the pre-updated data memory region or the first memory device the data constituting the data group at a certain timing exists, acquires data from the one in which the data exists and writes it into the second memory device of the second storage subsystem, and generates the certain timing repeatedly.

Abstract: A storage device includes a data-readable/writable storage medium, a data-readable/writable nonvolatile memory, and a controller which manages one of respective physical storage areas of the storage medium and the nonvolatile memory as being a logical storage area and which, in response to an access request from an external source, executes access to either one or both of the storage medium and the nonvolatile memory.

Abstract: A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.

Abstract: A method include a configuration definition creation step of writing configuration information on a primary site into a storage subsystem; a data transfer step of copying the configuration information, which is written into a storage device, to a storage subsystem in a secondary site over a network; a data reception step of receiving the transferred configuration information and storing it in the storage subsystem in the secondary site; and a configuration definition step of reading the stored configuration information and settings up a server in the secondary site.

Abstract: A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of

Abstract: One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.

Abstract: Systems and methods for storing data on a tape medium and coping with defective regions on the tape medium are provided. The method includes: writing a plurality of envelopes of data onto the tape medium, each envelope of data comprising a plurality of blocks of data; detecting a defective region of the tape medium; writing a boundary start field after the defective region, the boundary start field indicating that the defective region has been passed; and writing a boundary end field before the defective region of the tape medium, the boundary end field indicating that the defective region follows the boundary end field.

Abstract: The present invention provides a virtualized computing systems and methods for transitioning in real time between LONG SUPER-MODE and LEGACY SUPER-MODE in the x86-64 architecture. In doing so, a virtual machine, which relies on the traditional 32-bit modes, i.e., REAL MODE and PROTECTED MODE (V86 SUB-MODE, RING-0 SUB-MODE, and RING-3 SUB-MODE), is able to run alongside other applications on x86-64 computer hardware (i.e., 64-bit). The method of performing a temporary processor mode context switch includes the steps of the virtual machine monitor's setting up a “virtual=real” page, placing the transition code for performing the processor mode context switch on this page, jumping to this page, disabling the memory management unit (MMU) of the x86-64 computer hardware, modifying the mode control register to set either the LONG SUPER-MODE bit or LEGACY SUPER-MODE bit, loading a new page table, and reactivating the MMU of the x86-64 computer hardware.

Abstract: A method and apparatus for initialization of a double-sided memory module having a least one pair of mirrored pins. In one embodiment, the method includes the generation of an opcode to initialize a first side of the memory module according to a first side pin routing. In one embodiment, the opcode is written to a host address selected for the first side of the memory module according to a system host address to memory address mapping. In one embodiment, the opcode is altered if a routing of address pins of the opposed side of the memory module are interchanged with reference to the first side pin routing. Subsequently, a unique host address is selected to produce the altered opcode at the address pins of the opposed side of the memory module according to a defined host address to memory address mapping. Other embodiments are described and claimed.

Abstract: A method and software for analyzing a heap is described, in which a snapshot is made of a heap, which can be later analyzed by an analysis tool when a program that had run out of memory is no longer running. In one embodiment, an object allocated by the program is accessed and copied into a file, and an address of the object allocated by the process is recorded in association with an offset in the file of the copy of the object. The copy of the object copied into the file has preferably the same size as the object allocated by the process. A heap analysis tool may then be run on the objects copied into the file.

Abstract: A host computer HA1 or the like is provided with a target program 3 that receives the provision of logical volumes 212, a volume interface program 12A that provides an interface for the logical volumes 212 to the target program 3, and a volume filter program 12B that selects one logical volume from the copying source volume 212A and copying destination volume 212B, and provides the selected logical volume to the target program 3 via the volume interface program 12A.

Abstract: A method for managing virtual memory including placing a first virtual memory page in a physical memory page to create a virtual-to-physical memory mapping, associating a first page mapping cookie value with the virtual-to-physical memory mapping, determining whether the virtual-to-physical memory mapping is valid using the first page mapping cookie value, and performing a memory operation addressing the first virtual memory page if the virtual-to-physical memory mapping is valid.

Abstract: An apparatus and method utilize compressed cache lines that incorporate embedded prefetch history data associated with such cache lines. In particular, by compressing at least a portion of the data in a cache line, additional space may be freed up in the cache line to embed prefetch history data associated with the data in the cache line. By doing so, long-lived prefetch history data may essentially be embedded in a cache line and retrieved in association with that cache line to initiate the prefetching of additional data that is likely to be accessed based upon historical data generated for that cache line, and often with no little or no additional storage overhead.

Abstract: The enclosure 10 in which the storage control system 600 is constructed comprises a scale-out NAS head group 111 constituted by two or more NAS heads, and a scale-up NAS head 110H that is a higher performance NAS head than each of NAS head members 110L that are the NAS heads constituting the scale-out NAS group 111. The enclosure 10 permits insertion into general-purpose slots 104 in which the NAS head members 110L and another type of channel control unit 112 that differs from the NAS head members 110L are inserted. The scale-up NAS head 110H is mounted within the enclosure 10 in a different location from the general-purpose slots 104.

Abstract: A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.

Abstract: Disclosed is a storage system having storage devices from which storage areas are specified. Virtualization apparatuses allocate the storage areas as virtual volumes and processes I/O requests with respect to the virtual volumes. A controller is operable to change the allocation of storage areas to the virtual volumes. The controller is configured to send a request to some of the virtualization apparatuses to temporarily suspend processing of their I/O. When a virtualization apparatus receives such a request, it completes its pending I/O and temporarily suspends subsequent I/O requests, and sends a completion report to the controller. The controller then changes the allocation of storage areas to the virtual volumes.

Abstract: A memory agent may include a first port and a second port, wherein the memory agent is capable of detecting the presence of another memory agent on the second port. A method may include performing a presence detect operation on a first port of a memory agent, and reporting the results of the presence detect operation through a second port of the memory agent.

Abstract: A method and system are disclosed for recovering lost data with redundancy in an individual hard drive. A mirroring-type process is used in a single hard drive to maintain a backup copy of all data stored on that hard drive. The hard drive maintains two copies of the stored data on different storage media segments or partitions defined by separate read/write heads. In the event that a hard drive media defect or error occurs with respect to any of the data stored on a segment defined by one head, that data can be restored from the segment defined by the other head(s).