Abstract: Improved techniques and systems for accommodating TLB shootdown events in multi-processor computer systems are disclosed. A memory management unit (MMU) having a TLB miss handler and miss exception handler is provided. The MMU receives instructions relative to a virtual address. A TLB is searched for the virtual address, if the virtual address is not found in the TLB, secondary memory assets are searched for a TTE that corresponds to the virtual address and its associated context identifier. The context identifier is tested to determine if the TTE is available. Where the TTE is available, the TLB and secondary memory assets are updated as necessary and the method initiates memory access instructions. Where the TTE is unavailable, the method either resolves the unavailability or waits until the unavailability is resolved and then initiates memory access instructions, thereby enabling the desired virtual address information to be accessed.

Abstract: A method and system for striping across multiple cache lines to prevent false sharing. A first descriptor to correspond to a first data block is created. The first descriptor is placed in a descriptor ring according to a striping policy to prevent false sharing of a cache line of the computer system.

Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

Abstract: Methods and apparatus are provided for closely coupling a dedicated memory port to a processor core while allowing external components access to the dedicated memory. A processor core such as a processor core on a programmable chip is provided with dedicated read access to a dual ported memory. Write access is arbitrated between processor core write access and read/write access by external components. A dedicated memory port is particularly beneficial in digital signal processing applications.

Abstract: Transaction-based data storage is provided by a host server (130) for a tape storage device (160). Data associated with a transaction is received from a client (105, 110, 115) at the host server (130) and provided to a cache (164) of the tape storage device (160), for writing to the tape medium (168). To confirm that data has been actually written to the tape medium (168) and is not still in the cache (164), a tape medium position corresponding to an amount of tape medium needed to store the data from a transaction is calculated by the host server (130) when it receives the data based on the amount of data and the data capacity of storage blocks of the tape (168). The host server (130) periodically queries the tape storage device (160) to learn the current tape position, and concludes the transaction when the tape storage device has written past the calculated position.

Abstract: A technique for managing a cache memory coupled to an intermediate node's processor. Packets acquired by the intermediate node that are destined for processing by the processor are tracked, without the processor's intervention, to determine if the processor is lagging in processing the acquired packets. If so, data associated with unprocessed packets are pre-fetched from an external memory and placed in the cache memory without the processor's intervention. Moreover, packets destined for processing by the processor and placed into the cache memory are tracked, without the processor's intervention, to determine if the processor has, in fact, completed the processing of those packets. If so, data contained in the cache memory that is associated with the processed packets are invalidated, again without the processor's intervention.

Abstract: Methods and systems for operating automotive computing devices are described. In one embodiment, multiple object store pages are maintained in device SRAM that is configured to be battery backed in an event of a power loss. One or more object store pages are periodically flushed to device non-volatile memory to make room for additional object store pages. The frequency of object store page writes is tracked, and object store pages that are least frequently written to are flushed before object store pages that are more frequently written to. In addition, in the event of a power loss, the SRAM is battery backed.

Abstract: A system-on-a-chip is described herein. The system-on-a-chip includes a microprocessor, a non-volatile imperfect semiconductor memory device and a memory controller. The memory controller is configured to transfer device data between the microprocessor and the non-volatile semiconductor imperfect memory device.

Abstract: A method for modification of data in a card transaction system having a memory card and a reader for reading the card. The card has a first memory (RAM) and a second memory (EEPROM) with data locations occupied by data recordings. Each transaction involves the modification of at least one of the data locations or the addition of a new recording. The method reads the address of a free location from a previous control register located in a first fixed location in the EEPROM memory, writes the new modified recording or addition in the free location, repeat the steps for each new recording to be modified or added, and writes in a second fixed location in the EEPROM memory a new control register containing the addresses of free locations within the EEPROM memory to use in the next transaction.

Abstract: A method include a configuration definition creation step of writing configuration information on a primary site into a storage subsystem; a data transfer step of copying the configuration information, which is written into a storage device, to a storage subsystem in a secondary site over a network; a data reception step of receiving the transferred configuration information and storing it in the storage subsystem in the secondary site; and a configuration definition step of reading the stored configuration information and settings up a server in the secondary site.

Abstract: Methods and apparatus are provided for accessing the proper memory in processors having program and data memories with different sizes. In some embodiments, a processor is optimized for data access and has registers that are the same size as the data memories. When a program is compiled, some implementations identify when a pointer variable points to a piece of data (data memory) or a function (program memory) and synthesize different sized operations accordingly. The proper mode and size are assigned for each pointer. Methods of the present invention do not require annotation of functions. Existing code does not need to be modified and there is no opportunity to introduce errors. The invention does not require extra program memory to be located at directly accessible locations to store stub code.

Abstract: A processor includes controller circuitry operative to control the storage of a plurality of separate linked list data structures for protocol data units received by the processor. The linked list data structures are stored in memory circuitry associated with the processor, and the memory circuitry is arranged in a plurality of banks. The plurality of banks are configured to store respective ones of the plurality of separate linked list data structures, such that each of the plurality of banks stores a corresponding one of the plurality of separate linked list data structures. The linked list data structures are accessed in an alternating manner that reduces the likelihood of access conflicts between the banks. The processor may be configured as a network processor integrated circuit to provide an interface between a network and a switch fabric in a router or switch.

Abstract: A host computer HA1 or the like is provided with a target program 3 that receives the provision of logical volumes 212, a volume interface program 12A that provides an interface for the e logical volumes 212 to the target program 3, and a volume filter program 12B that selects one logical volume from the copying source volume 212A and copying destination volume 212B, and provides the selected logical volume to the target program 3 via the volume interface program 12A.

Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

Abstract: A method to write information to an information storage medium. The method creates one or more objects comprising information and provides a first one of those one or more objects. The method writes a header label to an information storage medium, where the header label comprises an object processing indicator. The method assigns a first sequence number to the first object and writes that first object to the information storage medium beginning at a first blockid and ending at a second blockid. The method writes a trailer label to the information storage medium, where that trailer label comprises an embedded object field count. The method writes an object information block to the information storage medium, where that object information block comprises the first sequence number, the first blockid, and the second blockid.

Abstract: A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.

Abstract: A method, system, and apparatus to reduce power consumption of a memory by actively asserting the CKE pin based at least in part on a LRU status of the rows in an active mode.

Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

Abstract: A computer system includes a main memory, at least one processor, and at least one level of cache. The system maintains reference history data with respect to each addressable page in memory, preferably in a page table. The reference history data is preferably used to determine which cacheable sub-units of the page should be pre-fetched to the cache. The reference history data is preferably an up or down counter which is incremented if the cacheable sub-unit is loaded into cache and is referenced by the processor, and decremented if the sub-unit is loaded into cache and is not referenced before being cast out. The reference counter thus expresses an approximate likelihood, based on recent history, that the sub-unit will be referenced in the near future.

Abstract: An SDRAM controller includes a service unit for receiving an SDRAM service request from at least one requester; a memory for storing instructions for performing a plurality of SDRAM transactions; and a lookup table of a sequence of addresses corresponding to at least a portion of the instructions stored in the memory, the portion of the instructions defining the SDRAM transaction. The service unit is configured to execute the SDRAM transaction based on the sequence of addresses in the lookup table. Also included is an arbiter for receiving service requests from multiple requestors to access the SDRAM, and another lookup table of identifiers corresponding to the multiple requestors, the identifiers stored in another sequence of addresses. The arbiter is configured to sequentially access each address in the other sequence of addresses, and grant service to a requestor based on an identifier stored in an address accessed.