Patents Examined by Shawn X. Gu
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Patent number: 10621106Abstract: A computer system includes a translation lookaside buffer (TLB) data cache and a processor. The TLB data cache includes a hierarchical configuration comprising a first TLB array, a second TLB array, a third TLB array, and a fourth TLB array. The processor is configured to receive a first address for translation to a second address, and determine whether translation should be performed using a hierarchical page table or a hashed page table. The processor also determines (using a first portion of the first address) whether the first array stores a mapping of the first portion of the first address in response to determining that the translation should be performed using the hashed page table, and retrieving the second address from the third TLB array or the fourth TLB array in response to determining that the first TLB array stores the mapping of the first portion of the first address.Type: GrantFiled: December 5, 2018Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: David Campbell, Dwain A. Hicks
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Patent number: 10606506Abstract: Provided are a computer program product, system, and method for releasing space allocated to a space efficient target storage in a copy relationship with a source storage. Source and target copy relationships indicate source data in the source storage to copy to target data in the target storage. The source copy relationship indicates source data that need to be copied to the target data before being updated, and the target copy relationship indicates target data tracks updated with data copied from corresponding source data. An operation is initiated that results in terminating the source and target copy relationships. Space allocated to the target data for the source and target copy relationships is released in response to determining that the target storage comprises the space efficient storage. The source and target copy relationships are removed.Type: GrantFiled: May 17, 2018Date of Patent: March 31, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theresa M. Brown, Nicolas M. Clayton, Nedlaya Y. Francisco, Suguang Li, Mark L. Lipets, Gregory E. McBride, Carol S. Mellgren, Raul E. Saba
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Patent number: 10607680Abstract: In an embodiment a semiconductor device may include a weakness detector configured to manage error occurrence information by dividing the memory device into a plurality of areas, to control a first refresh period for a first refresh request at each of the plurality of areas based on the error occurrence information and to generate a second refresh request for a second refresh address included in each of the plurality of areas based on the error occurrence information, and a refresh controller configured to generate a first refresh command according to the first refresh period and output the first refresh command to the memory device and to output a second refresh command and the second refresh address to the memory device according to the second refresh request and the second refresh address.Type: GrantFiled: May 21, 2018Date of Patent: March 31, 2020Assignee: SK hynix Inc.Inventors: Youngjae Jin, Joonwoo Kim, Youngook Song
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Patent number: 10606516Abstract: Systems and methods disclosed herein provide an I/O prioritization scheme for NVMe-compliant storage devices. Through an interface of an HBA driver, a user specifies a range of LBAs that map to a namespace. The user interface also designates a priority level for the namespace. Once the namespace is created, the HBA driver generates a queue of the designated priority level. The HBA driver also generates a table that maps the queue to the namespace. When the HBA driver receives a request to perform an I/O command that targets the namespace, the HBA driver adds the requested command to the queue. I/O commands targeting the namespace are processed in accordance with the designated priority level by the controller.Type: GrantFiled: August 13, 2018Date of Patent: March 31, 2020Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventor: Sumangala Bannur Subraya
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Patent number: 10599579Abstract: Cache on a persistent memory module is dynamically allocated as a prefetch cache or a write back cache to prioritize read and write operations to a persistent memory on the persistent memory module based on monitoring read/write accesses and/or user-selected allocation.Type: GrantFiled: June 25, 2018Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Karthik Kumar, Francesc Guim Bernat, Benjamin Graniello, Thomas Willhalm, Mustafa Hajeer
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Patent number: 10593383Abstract: Methods, systems, and devices for system-level timing budget are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.Type: GrantFiled: September 4, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventor: Kang-Yong Kim
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Patent number: 10592142Abstract: Transient mode for an application is toggled. Transient mode for an application executing in the computing environment is activated. Based on activating transient mode for the application, a plurality of memory accesses are processed as transient accesses. Based on processing the plurality of memory accesses, transient mode for the application is deactivated.Type: GrantFiled: September 30, 2016Date of Patent: March 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Gschwind, Christian Jacobi, Younes Manton, Anthony Saporito, Timothy J. Slegel
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Patent number: 10592165Abstract: There is disclosed techniques for queuing I/O requests on Mapped RAID. The techniques comprising queuing a pending I/O request in a queue. The techniques also comprising determining that sufficient credits are available to enable a number of storage devices of a plurality of storage devices in a Mapped RAID group to process the pending I/O request. The techniques further comprising processing the pending I/O request upon determining that there is sufficient credits.Type: GrantFiled: February 2, 2018Date of Patent: March 17, 2020Assignee: EMC IP Holding Company LLCInventors: Geng Han, Jibing Dong, Jian Gao, Xinlei Xu, Jamin Kang, Naizhong Chiu
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Patent number: 10579523Abstract: The subject matter described herein relates to a file system with adaptive flushing for an electronic device. The file system keeps data in memory much longer and its policy for flushing in-memory write cache to storage is application-aware and adaptive. More specifically, what parts of the cached data are ready for flushing could be determined according to the access characteristic of an application. In addition, when to do flushing can be selected flexibly at least partly based on user input interactions with an application of the electronic device or with the electronic device. Further, a multi-priority scheduling mechanism for scheduling data units that are ready to be flushed could be employed, which ensures fairness among applications and further improves flushing performance.Type: GrantFiled: August 15, 2014Date of Patent: March 3, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Jinglei Ren, Chieh-Jan Mike Liang, Thomas Moscibroda
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Patent number: 10572407Abstract: A data storage system may include one or more storage arrays. Each storage array may include a first set of solid-state drives and a first set of striped hard disk drives. Each solid-state drive of the first set of solid-state drives has a first data throughput and the set of stripe hard disk drives has a second data throughput. The second data throughput of the first set of striped hard disk drives is within a threshold throughput of the first data throughput. The data storage system also includes a processing device configured to receive an access request to write first data to the storage array and determine a read access frequency of the first data. The processing device may also be configured to determine a write access frequency of the first data and write the first data to the first set of solid-state drives or the first set of striped hard disk drives, based on the read access frequency and the write access frequency.Type: GrantFiled: August 11, 2017Date of Patent: February 25, 2020Assignee: Western Digital Technologies, Inc.Inventors: Jun Xu, Junpeng Niu, William Bernard Boyle, Jie Yu
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Patent number: 10564891Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.Type: GrantFiled: September 29, 2017Date of Patent: February 18, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Amir Shaharabany, Hadas Oshinsky
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Patent number: 10565064Abstract: One embodiment is related to a method for backing up virtual machines, comprising: determining whether virtual machines comprised in a backup policy group are to be backed up based on a present time and a backup schedule associated with the backup policy group; in response to a determination that the virtual machines comprised in the backup policy group are to be backed up, determining a data change ratio since a previous backup for each virtual machine comprised in the backup policy group; and backing up each virtual machine comprised in the backup policy group that has a data change ratio since the previous backup that meets a data change threshold associated with the backup policy group.Type: GrantFiled: February 1, 2018Date of Patent: February 18, 2020Assignee: EMC IP HOLDING COMPANY LLCInventor: Anupam Sharma
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Patent number: 10558386Abstract: An operation device according to an embodiment includes an operation instruction circuit, an operation circuit, a buffer and a storage area instruction circuit. The operation instruction circuit issues an operation instruction for an operation type of either one of a first operation and a second operation. The operation circuit performs an operation in accordance with the operation instruction, and outputs an intermediate operation result. The buffer stores the intermediate operation result. The storage area instruction circuit specifies an area within the buffer in Which the intermediate operation result is stored, according to the operation type.Type: GrantFiled: March 16, 2018Date of Patent: February 11, 2020Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hui Xu, Yasuki Tanabe, Toru Sano
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Patent number: 10558563Abstract: According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.Type: GrantFiled: June 25, 2018Date of Patent: February 11, 2020Assignee: Toshiba Memory CorporationInventor: Shinichi Kanno
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Patent number: 10558374Abstract: A system according to certain aspects may include a secondary storage controller computer configured to: in response to a first instruction to obtain a first secondary copy of a first data set from a secondary storage device(s), the first instruction associated with a first restore operation: instantiate a first restore thread on a processor of the secondary storage controller computer; using the first restore thread, retrieve the first secondary copy from the secondary storage device(s); and forward the retrieved first secondary copy to a primary storage subsystem for storage; and in response to a second instruction to obtain a second secondary copy of a second data set from the secondary storage device(s), the second instruction associated with a second restore operation: using the first restore thread, retrieve the second secondary copy from the secondary storage device(s); and forward the retrieved second secondary copy to the primary storage subsystem for storage.Type: GrantFiled: May 11, 2018Date of Patent: February 11, 2020Assignee: Commvault Systems, Inc.Inventors: Manoj Kumar Vijayan, Saurabh Agrawal, Deepak Raghunath Attarde
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Patent number: 10552077Abstract: Disclosed herein are techniques for managing partitions on a storage device. A method can include (1) identifying a storage capacity of the storage device, (2) generating a first data structure that defines a first partition on the storage device, where the first partition consumes a first amount of the storage capacity, and (3) generating a second data structure that defines a second partition on the storage device, where the second partition consumes at least a portion of a remaining amount of the storage capacity relative to the first amount. In response to receiving a shrink request directed to the first partition, the method can further include (4) identifying a first utilized area within the first partition that will no longer be utilized as a result of the shrink request, and (5) updating first information in the first data structure to indicate that the first utilized area is unutilized.Type: GrantFiled: September 29, 2017Date of Patent: February 4, 2020Assignee: Apple Inc.Inventor: Andrew W. Vogan
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Patent number: 10552086Abstract: Apparatus and method for managing shared resources in a data storage device such as a solid-state drive (SSD). In some embodiments, a non-volatile memory (NVM) has a population of semiconductor memory dies which are divided into die sets for different users. Each die set includes user garbage collection units (GCUs) for storage of user data blocks by the associated user and overprovisioned global GCUs to store user data blocks from the users of the other die sets. When an imbalance condition exists such that the workload traffic level of a first die set exceeds a workload traffic level of a second die set, at least one host I/O command for the first die set is offloaded for servicing using a selected global GCU of the second die set. The offloaded data may be subsequently transferred to the first die set after the imbalance condition is resolved.Type: GrantFiled: June 28, 2018Date of Patent: February 4, 2020Assignee: Seagate Technology LLCInventors: David W. Claude, Steven S. Williams, Stacey Secatch
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Patent number: 10552039Abstract: A storage control apparatus including a memory and a processor coupled to the memory and the processor configured to execute a process, the process including storing, in the memory, management information including an operation history for a storage region of a storage device, specifying at certain timing, from the management information, a first operation that has been executed to set a configuration of the storage region to a configuration at the certain timing, determining a second operation from among operations, in the management information, that precede the execution of the first operation and that target the storage region, deleting the second operation from the management information, and transmitting the management information after the deletion to a management apparatus that manages a state of the storage region of the storage device.Type: GrantFiled: December 22, 2017Date of Patent: February 4, 2020Assignee: FUJITSU LIMITEDInventors: Natsumi Nakata, Toshiharu Makida
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Patent number: 10545867Abstract: A device, method, and a data storage medium, configured to enhance an item access bandwidth and atomic operation are provided. The device comprises: a comparison module, a cache, and a distribution module; wherein the comparison module is configured to receive a query request from a service side, determine whether an address pointed to by the query request and an item address stored in the cache are identical. If so, and a valid identifier vld is valid, the comparison module is configured to directly return the item data stored in the cache to the service side without initiating a request for looking up an off-chip memory, so as to reduce a frequency of accessing the off-chip memory. If not, the comparison module is configured to initiate a request for looking up the off-chip memory, so as to process, according to a first preconfigured rule, item data returned by the off-chip memory.Type: GrantFiled: May 10, 2016Date of Patent: January 28, 2020Assignee: SANECHIPS TECHNOLOGY CO., LTD.Inventors: Chuang Bao, Zhenlin Yan, Chunhui Zhang, Kang An
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Patent number: 10545677Abstract: A traffic manager for a distributed data storage system includes an iterative spike identifier to identify N levels of traffic spikes in traffic data on an account basis in a distributed data storage system, where N is greater than zero. A traffic cycle identifier selectively identifies cyclic traffic spikes in at least one of the N levels of traffic spikes for each of a plurality of accounts using autocorrelation and peak detection. A partition manager communicates with the traffic cycle identifier and selectively partitions one of the plurality of accounts based on based on the autocorrelation and the peak detection.Type: GrantFiled: June 18, 2018Date of Patent: January 28, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Sumadhur Reddy Bolli, Liang Xie, Dengkui Xi, Arild Einar Skjolsvold, Xinhua Ji, Dengyao Mo, Marcus Kimball Swenson