Patents Examined by Shawn X. Gu
  • Patent number: 11036415
    Abstract: A computer-implemented method, according to one embodiment, is for managing block calibration operations. The computer-implemented method includes: determining a type of calibration procedure to apply to a block of memory, and assigning the calibration type to the block. A calibration level to assign to the block is also determined, and thereafter the calibration level is assigned to the block. Moreover, the block is assigned to one of two or more calibration queues based on the calibration type and calibration level associated with the block. A different priority level is assigned to each of the calibration queues, and the priority levels determine an order in which blocks assigned to the calibration queues are calibrated.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Roman Alexander Pletka, Aaron Daniel Fry, Timothy Fisher, Nikolas Ioannou, Charalampos Pozidis, Radu Ioan Stoica, Sasa Tomic
  • Patent number: 11016904
    Abstract: A storage device includes a controller and a memory. In response to a request of a host, the controller generates: (A) a first list as a result of counting: (1) the number of first page numbers included in a first range among page numbers included in a logical address received from the host and (2) the number of second page numbers included in a second range not overlapping the first range, (B) generates a second list as a result of respectively grouping the first page numbers and the second page numbers based on the first list, and (C) translates the logical address to a physical address based on the second list and the first map data. The memory stores the first map data to be provided to the controller. The first map data matches the first page numbers and the second page numbers with respective physical addresses.
    Type: Grant
    Filed: August 17, 2019
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongwon Cho, Hyeonwu Kim, Seok-Won Ahn
  • Patent number: 11016700
    Abstract: Accumulating application-level statistics in a storage system that includes a plurality of block storage devices, including: identifying, from data stored on a block storage device, one or more sub-regions of the data stored on the block storage device that are associated with an application; and compiling, from statistics maintained for each of the one or more sub-regions of the stored data associated with the application, cumulative statistics for the application.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 25, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Steven Hodgson, Ronald Karr
  • Patent number: 11016897
    Abstract: Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by a plurality of processing elements which operate on the set of many-core hardware processors. The stream of tuples to be processed by the plurality of processing elements which operate on the set of many-core hardware processors may be received. A tuple-processing hardware-route on the set of many-core hardware processors may be determined based on a cache factor associated with the set of many-core hardware processors. The stream of tuples may be routed based on the tuple-processing hardware-route on the set of many-core hardware processors. The stream of tuples may be processed by the plurality of processing elements which operate on the set of many-core hardware processors.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Cook, Cory J. Kleinheksel, David M. Koster, Jason A. Nikolai
  • Patent number: 11010061
    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
  • Patent number: 10997026
    Abstract: A method is disclosed for destaging data to a storage device set that is arranged to maintain M replicas of the data, the storage device set having M primary storage devices and N secondary storage devices, the method comprising: detecting a destage event; and in response to the destage event, destaging the data item that is stored in a journal, the destaging including: issuing M primary write requests for storing the data item, each of the M primary write requests being directed to a different one of the M primary storage devices; in response to detecting that L of the primary write requests have failed, issuing L secondary write requests for storing the data item, each of the L secondary write requests being directed to a different secondary storage device; updating a bitmap to identify all primary and secondary storage devices where the data item has been stored.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 4, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Lior Kamran, Alex Soukhman, Hillel Costeff
  • Patent number: 10990531
    Abstract: Systems, apparatuses and methods may provide for technology that in response to one or more of an installation of an application or a modification to the application, generates a lookup key based on a first file that is associated with the application, determines that the lookup key is to be transmitted to a server, and determines whether to store at least a portion of the first file in a memory cache based on a first frequency indicator associated with the first file from the server.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Fredrick Odhiambo, Maximillan Domeika
  • Patent number: 10983875
    Abstract: Recovery points can be used for replicating a virtual machine and reverting the virtual machine to a different state. A filter driver can monitor and capture input/output commands between a virtual machine and a virtual machine disk. The captured input/output commands can be used to create a recovery point. The recovery point can be associated with a bitmap that may be used to identify data blocks that have been modified between two versions of the virtual machine. Using this bitmap, a virtual machine may be reverted or restored to a different state by replacing modified data blocks and without replacing the entire virtual machine disk.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 20, 2021
    Assignee: Commvault Systems, Inc.
    Inventors: Amit Mitkar, Andrei Erofeev, Amit Bhaskar Ausarkar, Ajay Venkat Nagrale
  • Patent number: 10983722
    Abstract: A data storage device includes a nonvolatile memory device, a storage controller and a mapping controller. The nonvolatile memory device stores an execution code that controls operations of the data storage device. The storage controller uploads and stores the execution code from the nonvolatile memory device to a host memory buffer included in an external host device, and downloads the execution code in realtime from the host memory buffer to execute the execution code that is downloaded from the host memory buffer. The mapping controller manages a mapping table including mapping relations between the execution code and host addresses of the host memory buffer at which the execution code is stored. A speed of accessing the execution code is increased and performance of the data storage device is enhanced by using the host memory buffer as storage of the execution code to control the operation of the data storage device.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Seok Kim, Walter Jun
  • Patent number: 10977184
    Abstract: A method for managing memory access for implementing at least one layer of a convolutional neural network is provided. The method comprises predicting an access procedure in relation to a portion of memory based on a characteristic of the convolutional neural network. In response to the prediction, the method comprises performing an operation to obtain and store a memory address translation, corresponding to the portion of memory, in storage in advance of the predicted access procedure. An apparatus is provided comprising at least one processor and storage. The apparatus is configured to predict an access procedure in relation to a portion of memory which is external to the processor. In response to the prediction, the apparatus is configured to obtain and store a memory address translation corresponding to the portion of memory in storage in advance of the predicted access procedure.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 13, 2021
    Assignee: Apical Limited and Arm Limited
    Inventors: Sharjeel Saeed, Daren Croxford, Graeme Leslie Ingram
  • Patent number: 10969980
    Abstract: A processor includes a processing core; a filter register to store a first permissions filter; and a memory management unit (MMU), coupled to the processing core, the filter register and a first peripheral device associated with the first permissions filter, wherein the MMU comprises a logic circuit to manage a shared page table comprising entries corresponding to the processing core and the first peripheral device, wherein the logic circuit is to; receive a memory access request for a first page of memory from the first peripheral device; determine whether the set of permission bits of the first entry match a first combination of bits of the first permissions filter; grant the memory access request if the set of permission bits match the first combination of bits of the first permissions filter; and cause a page fault if the set of permission bits do not matching the first combination of bits.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: David Hansen, Ashok Raj
  • Patent number: 10949122
    Abstract: A computer-implemented method, according to one embodiment, includes: determining a current temperature associated with an intended storage location in memory for data in a write request, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Saravanan Sethuraman, Venkata K. Tavva, Adam J. McPadden, Hillery Hunter
  • Patent number: 10949352
    Abstract: A cache is shared by a first and second processor, and is divided into a first cache portion corresponding to a first requestor identifier (ID) and a second cache portion corresponding to a second requestor ID. The first cache portion is accessed in response to memory access requests associated with the first requestor ID, and the second cache portion is accessed in response to memory access requests associated with the second requestor ID. A memory controller communicates with a shared memory, which is a backing store for the cache. A corresponding requestor ID is received with each memory access request. Each memory access request includes a corresponding access address identifying a memory location in the shared memory and a corresponding index portion, wherein each corresponding index portion selects a set in a selected cache portion of the first and second cache portions selected based on the received corresponding requestor ID.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 16, 2021
    Assignee: NXP USA, Inc.
    Inventor: Paul Kimelman
  • Patent number: 10942850
    Abstract: A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 9, 2021
    Assignee: Apple Inc.
    Inventors: John G. Dorsey, Aditya Venkataraman, Bryan R. Hinch, Daniel A. Chimene, Andrei Dorofeev, Constantin Pistol
  • Patent number: 10936437
    Abstract: Snapshot policy event logs are maintained containing timestamps associated with changes to the snapshot policy over time. Storage group event logs are maintained for each storage group associated with the snapshot policy containing timestamps associated with changes to the storage group over time. Snapshot compliance is calculated by creating a timeline of the snapshot policy and creating timelines for each of the storage groups associated with the snapshot policy. The snapshot policy timeline and storage group timelines are intersected to calculate how many snapshots should have been created for each storage group associated with the snapshot policy during each snapshot policy timeline interval. The sum of all snapshots that should have been created and still be maintained at a particular point in time is compared with an actual number of snapshots maintained for the storage groups by the storage system at that point in time.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventor: Thiago Santos
  • Patent number: 10929030
    Abstract: A computer comprises a controller and a storage apparatus which is configured to provide a storage area for storing data. The controller and the storage apparatus have a function of achieving encryption and decryption of data through use of an encryption key. The computer is configured to: execute encryption key setting processing for setting the encryption key in the controller and the storage apparatus so that the controller holds the same encryption key as the encryption key of the storage apparatus; and determine whether to enable the function of any one of the controller and the storage apparatus, based on load states of the controller and the storage apparatus when an I/O request is received.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: February 23, 2021
    Assignee: HITACHI, LTD.
    Inventor: Koji Washiya
  • Patent number: 10921993
    Abstract: Embodiments include systems, methods, and computer program products to perform an operation for enabling multipath I/O for logical volume backed virtual disks through redundant virtual I/O servers (VIOSs) on a computing system. The operation generally includes creating, from a physical storage device, a logical volume on a first VIOS. The logical volume on the first VIOS is activated in a first access mode. The operation also includes importing the logical volume to a second VIOS. The logical volume on the second VIOS is activated in a second access mode different from the first access mode. The operation further includes mapping the logical volume on the first and second VIOSs as a backing storage device for at least one logical partition hosted on the computing system.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: February 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Venkata N. S. Anumula, Sudhir Maddali, Sanket Rathi
  • Patent number: 10922265
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a transaction request to perform a transaction with the memory, the transaction request including a synchronization indication to indicate utilization of transaction synchronization to perform the transaction. Embodiments may include sending a request to a caching agent to perform the transaction, receiving a response from the caching agent, the response to indicate whether the transaction conflicts or does not conflict with another transaction, and performing the transaction if the response indicates the transaction does not conflict with the other transaction, or delaying the transaction for a period of time if the response indicates the transaction does conflict with the other transaction.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Nicolae Popovici, Thomas Willhalm
  • Patent number: 10921997
    Abstract: An information capture device includes a camera member, a storage unit, a network module and a processing unit. The camera member captures an ambient environment to generate an environment image stream of the ambient environment. The storage unit has a storage space. The network module receives a cyclic recording policy through a network, wherein the cyclic recording policy includes an activation instruction and a storage capacity setting. The processing unit calculates a designated storage capacity according to the storage capacity setting and a total capacity of the storage space, detects a spare capacity of the storage space according to the designated storage capacity, limits the designated storage capacity to be used exclusively for the cyclic recording process, and activates and executes the cyclic recording process according to the activation instruction when the spare capacity satisfies the designated storage capacity.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: February 16, 2021
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Chien-Chih Hu
  • Patent number: 10921990
    Abstract: Techniques involve determining a first remaining lifetime of a flash device at a first time based on a warranty period, a factor of the number of writes per unit of time, and the number of executed writes for the flash device. The techniques further involve obtaining a second remaining lifetime at a second time prior to the first time, the second remaining lifetime being determined at the second time based on the warranty period, the factor of the number of writes per unit of time, and the number of executed writes. The techniques further involve determining a first lifetime decay rate based on the first and second remaining lifetimes. In addition, the techniques may determine a first predicted remaining lifetime based on the first lifetime decay rate. Accordingly, a remaining lifetime can be predicted based on the usage trend thereof.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Yang Zhang, Hao Wang, Jiang Tan