Abstract: A safety communication device includes: a safety layer parameter acquisition part to acquire a reception bit rate of safety layer data being received per unit time; a threshold value setting part to set a request error rate requested as an upper limit of a bit error rate of the safety layer data received per unit time, on the basis of a request value corresponding to a bit error rate request being requested as an upper limit of an error occurrence probability per bit during data communication in a non-safety network, and a reception bit rate; and a safety monitoring control part to compare the bit error rate of the safety layer data received within a unit time, with the request error rate, and to perform safety control on the basis of a comparison result.

Abstract: Provided is a transmission method executed by a transmitting apparatus to transmit a content to a plurality of terminals. The content having transmission count information indicating a number of times the content is to be transmitted by the transmitting apparatus. The transmission method including a first transmission step of generating and transmitting a first transmission signal which transfers at least a first portion of a plurality of data packets including a plurality of content packets, storing data of the content therein, and a plurality of parity packets, generated from the content packets, and a second transmission step of, when the transmission count information of the content indicates a plurality of times, generating a second transmission signal including at least a second portion of the plurality of data packets, and transmitting the second transmission signal during a period which differs from a period during which the first transmission signal is transmitted.

Abstract: Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to read information from a secondary device about whether the secondary device supports parity-protected data communications. The primary device can be configured to selectively send or receive parity-protected data communications depending on a capability of the secondary device to support parity.

Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.

Abstract: A system includes a first node, a second node, and a third node, wherein the first node establishes a wireless communication link with the second node to perform wireless communication, and forwards connection information of the wireless communication to the third node; and the third node receives, by listening on the wireless communication link based on the connection information, transmission data sent by the second node to the first node. If an error occurs when the third node receives the transmission data sent by the second node to the first node, the third node interferes with the first node's reception of the transmission data sent by the second node, so that an error is caused when the first node receives the transmission data sent by the second node, and the second node is triggered to perform retransmission.

Abstract: Error correction in network packets using soft information and modified payloads are disclosed herein. The method can include extracting soft information from copies of a network packet, using the extracted soft information to select K positions in a payload of the network packet, the payload with uncertain values of bits, the selected K positions having largest levels of uncertainty, changing one or more of the uncertain values at the K positions to a selected combination of values to transform the payload to a modified payload of the network packet, generating an error detection code for the modified payload and when the generated error detection code for the modified payload matches the error detection code for the network packet, using the modified payload as a corrected network packet and processing the next network packet.

Abstract: A method and an optical sensor are described herein. The optical sensor may include a communication interface for receiving data from a control unit and for transmitting data to the control unit, a storage unit with at least one register for storing data, and a CRC generator for generating a CRC checksum. The optical sensor may be configured in such a way that when data stored in the storage unit is to be transmitted to the control unit, the communication interface receives from the control unit a device address specific to the optical sensor and an address of a register in which the data to be transmitted is stored. The CRC generator may be initialized using the device address received from the communication interface and/or the register address received from the communication interface, before the CRC generator generates a CRC checksum for the data to be transmitted.

Abstract: Method and apparatus for intelligent caching, protection and transfers of data between a cache and a main memory in a data storage environment, such as but not limited to a solid-state drive (SSD). A main memory (MM) has non-volatile memory (NVM) cells configured for persistent storage of user data. A fast response cache (FRC) has NVM cells configured to provide storage of first data prior to transfer to the MM. A write cache (WC) has NVM cells configured to provide storage of second data prior to transfer to the MM. A controller directs input data to either the FRC or the WC. A first type of error correction encoding (ECC1) is applied to the first data and a different, second type of error correction encoding (ECC2) is applied to the second data. Data may be sent from the FRC to the MM either directly or through the WC.

Abstract: A storage device is provided. The storage device includes a memory device including a memory cell array configured to store metadata and main data and a storage controller configured to access the memory device and control the memory device, wherein the storage controller is configured to read data from the memory device at a speed adaptively varying to a first read speed or a second read speed according to a state of the memory device, the second read speed being faster than the first read speed.

Abstract: Provided is a design method and apparatus for quasi-cyclic low-density parity-check (LDPC) encoding. The method includes: performing LDPC encoding on a K-bit information sequence to be encoded according to a parity check matrix of a quasi-cyclic LDPC code to obtain an N-bit LDPC encoded sequence, where the parity check matrix is determined according to a basic matrix and a lifting size Z, and the basic matrix is determined according to the lifting size Z and a coefficient matrix, where K is a positive integer, N is an integer greater than K, and Z is a positive integer.

Abstract: Disclosed is a method for processing code blocks as implemented by a baseband processor. The method involves performing a cyclic redundancy check on decoded and deinterleaved code blocks until one fails its CRC check. On first failure the baseband processor requests a retransmission of the code blocks and resumes CRC checks on the retransmitted code blocks, beginning at the code block that had failed. In the event of subsequent failures, the baseband processor performs a soft combine on the failed retransmitted block with its original transmitted counterpart. Only if the soft combined code block fails does the baseband processor request another retransmission. In this case, subsequent CRC failures result in soft combines of three corresponding code words, making the process more robust. The method reduces the number of retransmissions as well as the computing resources needed for processing incoming code blocks.

Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: Systems, methods, and computer-readable media are provided for utilizing distributed erasure encoding in a redundant array of independent disks (RAID) system. An example method can include generating a plurality of virtual redundant array of independent disk (vRAID) stripes, each of the plurality of vRAID stripes including a segment having a plurality of data, each of the plurality of data including metadata, the metadata including a checksum of a corresponding data of the plurality of data, distributing the segment of each of the plurality of vRAID stripes over a plurality of virtual nodes, mapping at least one of logical files, volumes, or objects to the plurality of data chunks and the at least one parity chunk of the plurality of vRAID stripes to avoid write-hole issues, and verifying data integrity of the corresponding data of the plurality of data using the checksum of the corresponding data.

Abstract: A method for compressing pre-compressed data used in a reconfigurable processor, where the pre-compressed data includes a number of data blocks, obtains a current data block, calculates a current checking code of the current data block, and compares the current checking code with an immediately-previous checking code. A tag of the current data block is marked as a first tag if the current checking code and the immediately-previous checking code are different, and is marked as a second tag if the current checking code and the immediately-previous checking code are the same. Only data blocks whose tags are the first tags are saved. A related device for compressing data, and a method and a device for decompressing data are also provided.

Abstract: Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair.

Abstract: Embodiments of the present disclosure relate to a binary clustered forward error correction encoding scheme. Systems and methods are disclosed that define binary clustered encodings of the media packets from which forward error correction (FEC) packets are computed. The different encodings specify which media packets in a frame are used to compute each FEC packet (a frame includes M media packets). The different encodings may be defined based on the quantity of media packets in a frame, M?floor(2N), where each bit of the binary representation of N is associated with a different cluster pair encoding of the media packets. Each cluster pair includes a cluster for which the bit=0 and a cluster for which the bit=1. Computing FEC packets using at least two cluster pair encodings provides redundancy for each media packet, thereby improving media packet recovery rates.

Abstract: Systems and methods are disclosed for detecting shingled overwrite errors. When a read error is encountered when reading from shingled recording tracks, a processor may determine whether the read error is an error caused by shingled overwriting. The processor may determine whether the read error is caused by shingled overwriting by determining read signal quality of one or more sectors preceding the read error, such as based on a bit error count or bit error ratio (BER), and comparing the read signal quality to a threshold value. The processor may determine that the read error is caused by shingled overwriting when the read signal quality value is lower than the threshold.

Abstract: Provided are systems and methods for adaptive payload extraction and retransmission in wireless data communications. An example method commences with transmitting a network packet to a receiver via a communication channel. The method further includes receiving a further network packet including a further payload. The method continues with determining, based on the payload and the further payload, an error vector. The method includes generating, based on the error vector, a plurality of indices. An index of the plurality of indices corresponds to a portion of a plurality of non-overlapping portions of the payload. The method further continues with selecting, based on the error vector, at least one index from the plurality of indices. The method includes sending, to the receiver via the communication channel, a further network packet. The further network packet includes the selected index and a portion of the payload corresponding to the selected index.

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.