Patents Examined by Sheng-Bai Zhu
  • Patent number: 12261197
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A dielectric layer is formed on the bottom electrode. A first top electrode layer is deposited on the dielectric layer by a first deposition process. A diffusion barrier layer is deposited on the first top electrode layer by a second deposition process different from the first deposition process. A second top electrode layer is deposited on the diffusion barrier layer by a third deposition. The third deposition process is the same as the first deposition process.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Hai-Dang Trinh, Fa-Shen Jiang
  • Patent number: 12262563
    Abstract: A pixel cell is formed on a semiconductor substrate having a front surface. The pixel cell includes a photodiode, a floating diffusion region, and a transfer gate. The photodiode is disposed in the semiconductor substrate. The floating diffusion region includes a first doped region disposed in the semiconductor substrate, wherein the first doped region extends from the front surface to a first junction depth in the semiconductor substrate. The transfer gate is configured to selectively couple the photodiode to the floating diffusion region controlling charge transfer between the photodiode and the floating diffusion region. The transfer gate includes a planar gate disposed on the front surface of the semiconductor substrate and a pair of vertical gate electrodes. Each vertical gate electrode extending a gate depth from the planar gate into the semiconductor substrate. The first junction depth is greater than the gate depth.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 25, 2025
    Assignee: OmniVision Technologies, Inc.
    Inventors: Shiyu Sun, Yuanwei Zheng, Gang Chen, Sing-Chung Hu, Armin Yazdani
  • Patent number: 12255176
    Abstract: A microelectronic assembly may include a semiconductor wafer having first and second surfaces extending in first and second directions, the semiconductor wafer having network nodes connected to one another via local adjacent connections each extending in only one of the first and second directions, and an interconnection structure comprising a low-loss dielectric material and having first and second opposite surfaces extending in third and fourth directions each oriented at an oblique angle relative to the first and second directions, the interconnection structure having local oblique connections each extending in only one of the third and fourth directions. The semiconductor wafer may be directly bonded to the interconnection structure such that each of the network nodes is connected with at least one of the other network nodes, without use of conductive bonding material, through at least one of the local adjacent connections and at least one of the local oblique connections.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: March 18, 2025
    Assignee: Adeia Semiconductor Technologies LLC
    Inventors: Javier A. DeLaCruz, Richard E. Perego
  • Patent number: 12249600
    Abstract: RC-network components that include a substrate and capacitor having a thin-film top electrode portion at a surface on one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion by an insulating layer, and a set of one or more bridging contacts passing through openings in the insulating layer. The bridging contacts electrically interconnect the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The openings are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts have an elongated cross-sectional shape.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: March 11, 2025
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yohei Yamaguchi, Yasuhiro Murase, Stéphane Bouvier
  • Patent number: 12211850
    Abstract: An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 28, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Rakesh Dimri, Badarish Mohan Subbannavar, Somasekar J
  • Patent number: 12199032
    Abstract: According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: January 14, 2025
    Assignee: KIOXIA CORPORATION
    Inventor: Hisashi Kato
  • Patent number: 12191344
    Abstract: A discharge protection semiconductor structure is provided that includes a substrate, a well positioned on the substrate, a first contact diffusion and a second contact diffusion, the first contact diffusion and the second contact diffusion positioned on the top side of the well, and a resistor positioned between the first contact diffusion and a second contact diffusion.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: January 7, 2025
    Assignee: Nexperia B.V.
    Inventor: Hans-Martin Ritter
  • Patent number: 12166063
    Abstract: An optoelectronic device includes an array of germanium-based photodiodes including a stack of semiconductor layers, made from germanium, trenches, and a passivation semiconductor layer, made from silicon. Each photodiode includes a silicon-germanium peripheral zone in the semiconductor portion formed through an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of the semiconductor portion.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: December 10, 2024
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Louis Ouvrier-Buffet, Abdelkader Aliane, Jean-Michel Hartmann, Julie Widiez
  • Patent number: 12150324
    Abstract: A display device includes a substrate, a plurality of pixels above the substrate, each of the plurality of pixels including a first electrode, a light emitting layer above the first electrode, and a second electrode above the light emitting layer, a display region including the plurality of pixels, a first organic insulating layer located between the substrate and the light emitting layer, and a sealing layer above the second electrode and covering the plurality of pixels. The first organic insulating layer includes a first opening part surrounding the display region, the sealing layer has a first inorganic insulating layer, a second organic insulating layer and a second inorganic insulating layer, the first inorganic insulating layer and the second inorganic insulating layer cover the first opening part, a second opening part passing through the first inorganic insulating layer and the second inorganic insulating layer.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: November 19, 2024
    Assignee: Japan Display Inc.
    Inventors: Akinori Kamiya, Kota Makishi
  • Patent number: 12142604
    Abstract: According to one embodiment, a first P-type transistor with a gate is coupled to a first node, and a drain is coupled to a second node. A first N-type transistor with a gate is coupled to the first node, and a drain is coupled to the second node. A second P-type transistor with a gate is coupled to the second node, and a drain is coupled to a third node. A second N-type transistor with a gate is coupled to the second node, and a drain is coupled to the third node. The first P-type transistor is smaller than the first N-type transistor. The second N-type transistor is smaller than the second P-type transistor. The second N-type transistor is smaller than the first N-type transistor.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: November 12, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama
  • Patent number: 12142634
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: November 12, 2024
    Assignee: Sony Group Corporation
    Inventors: Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani, Titash Rakshit, Peter Chang, Willy Rachmady
  • Patent number: 12136622
    Abstract: A bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first bipolar junction transistor. The first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip includes a second diode and a second bipolar junction transistor. The second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor. The second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: November 5, 2024
    Assignee: Amazing Microelectronic Corp.
    Inventors: Tun-Chih Yang, Zi-Ping Chen, Kun-Hsien Lin
  • Patent number: 12132042
    Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ching Huang, Sheng-Fu Hsu, Hao-Hua Hsu, Pin-Chen Chen, Lin-Yu Huang, Yu-Chang Jong
  • Patent number: 12127431
    Abstract: The present disclosure provides an OLED array substrate, a display panel and a display device. The OLED array substrate includes a first display region and a second display region; the first display region is adjacent to the second display region, and includes first OLED pixels arranged in an array; the second display region includes second OLED pixels arranged in an array; a pixel density of the second OLED pixels is less than a pixel density of the first OLED pixels; second pixel driving units of second OLED pixels and first pixel driving units of first OLED pixels in a same row are connected to a same first-type scan line, there is at least one second-type scan line between two adjacent first-type scan lines; one second-type scan line is only connected to first pixel driving units of first OLED pixels in a same row.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: October 22, 2024
    Assignee: Kunshan Go-Visionox Opto-Electronics Co., Ltd.
    Inventors: Miao Chang, Lu Zhang, Siming Hu, Zhenzhen Han
  • Patent number: 12113058
    Abstract: A display device includes a substrate including a display area and a non-display area; a semiconductor layer including a source area, a channel area, and a drain area and disposed in the non-display area of the substrate; a gate electrode overlapping the channel area of the semiconductor layer; a gate insulating layer disposed between the gate electrode and the channel area of the semiconductor layer; a source electrode electrically connected to the source area of the semiconductor layer; and a drain electrode electrically connected to the drain area of the semiconductor layer, wherein a lateral side of the gate electrode overlaps the drain electrode.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: October 8, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kang Moon Jo, An Su Lee, June Whan Choi
  • Patent number: 12107044
    Abstract: Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Marie Krysak, Kevin L. Lin, Robert Bristol, Charles H. Wallace
  • Patent number: 12074036
    Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen
  • Patent number: 12068268
    Abstract: A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: August 20, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Morio Iwamizu
  • Patent number: 12068159
    Abstract: Methods and apparatus for laser patterning leverage mask trench debris removal techniques to form etch singulation trenches. In some embodiments, the method includes forming a mask layer on the wafer, forming a pattern in the mask layer using a laser of a laser assembly where the pattern allows singulation of the wafer by deep etching and forms a trench in the mask layer with a laser beam which has a process point at a bottom of the trench, directing gas nozzles that flow a pressurized gas at the process point in the trench as the pattern is formed with a gas flow angle relative to the process point and evacuating debris from the trench using an area of negative pressure where the gas flow from gas nozzles and the area of negative pressure are in fluid contact and are confined within a cylindrical housing.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: August 20, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Karthik Narayanan Balakrishnan, Jungrae Park, Arunkumar Tatti, Sriskantharajah Thirunavukarasu, Eng Sheng Peh
  • Patent number: 12068325
    Abstract: A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X?1)-contacted poly pitch (CPP) circuit, which is (X?1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X?1)-CPP circuit, X being an integer greater than 1.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: August 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jung Ho Do