Abstract: An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. The metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an I/O channel by the ESD protection device and thereby improve the performance of a high-speed circuit that uses the I/O channel.

Abstract: Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.

Abstract: An organic light emitting diode display device includes a substrate having an emitting area and a non-emitting area. An insulating layer is on the substrate, and the insulating layer includes a plurality of convex portions, a plurality of connecting portions and at least one wall in the emitting area. A height of the at least one wall is greater than a height of the plurality of convex portions. A first electrode is on the substream, emitting layer is on the first electrode, a second electrode is on the emitting layer. The first electrode, the emitting layer and the second electrode constitute a light emitting diode.

Abstract: A microelectronic assembly may include a semiconductor wafer having first and second surfaces extending in first and second directions, the semiconductor wafer having network nodes connected to one another via local adjacent connections each extending in only one of the first and second directions, and an interconnection structure comprising a low-loss dielectric material and having first and second opposite surfaces extending in third and fourth directions each oriented at an oblique angle relative to the first and second directions, the interconnection structure having local oblique connections each extending in only one of the third and fourth directions. The semiconductor wafer may be directly bonded to the interconnection structure such that each of the network nodes is connected with at least one of the other network nodes, without use of conductive bonding material, through at least one of the local adjacent connections and at least one of the local oblique connections.

Abstract: A semiconductor structure manufacturing method includes that a substrate is provided, in which the substrate includes a substrate layer and a plurality of bit line structures arranged on the substrate layer in a first direction, the substrate layer includes shallow trench isolation structures, active areas, and a plurality of word line structures arranged in a second direction, and two adjacent bit line structures and two adjacent word line structures define a conductive contact region, and the conductive contact region exposing part of a corresponding active area; a conducting layer is formed between the bit line structures, the conducting layer covering the substrate layer, and the conducting layer extending along the first direction; part of the conducting layer is removed with the conducting layer corresponding to the conductive contact region retained to form first capacitor wires; and an isolation layer is formed, which fills gaps between the first capacitor wires.

Abstract: The present description concerns an electronic device comprising a stack of a Schottky diode and of a bipolar diode, connected in parallel by a first electrode located in a first cavity and a second electrode located in a second cavity.

Abstract: According to the disclosure, highly integrated memory cells and a semiconductor device having the same are provided. According to an embodiment, a semiconductor device comprises a plurality of memory cells vertically stacked on a base substrate, each of the plurality of memory cells includes, a bit line vertically oriented from the base substrate, a capacitor horizontally spaced apart from the bit line, an active layer horizontally oriented between the bit line and the capacitor, a word line positioned on at least one of a top surface and bottom surface of the active layer and horizontally extending in a direction crossing the active layer, and a capping layer positioned between the word line and the bit line and including, at least, a low-k material and an air gap.

Abstract: A display device may include a plurality of pixel electrodes arranged in a matrix along a first direction and a second direction perpendicular to each other. A plurality of light-emitting layers overlap with the respective plurality of pixel electrodes. A plurality of carrier generation layers are separated from one another. Each of the plurality of carrier generation layers continuously overlap with two of the plurality of light-emitting layers. The two are next to each other in a direction oblique to both the first direction and the second direction. A common electrode is opposed to the plurality of pixel electrodes.

Abstract: A method of producing a light source device includes providing a light emitting device having a substrate including a base member that includes a bottom surface and a recess. The substrate further including a wiring portion in the recess. The method further including providing a support substrate having a support base member, a first wiring pattern on a top surface of the support base member and including a joining region, and an insulating region, and applying a solder member such that the solder member on the insulating region has a volume larger than that of the solder member on the joining region. The light emitting device is placed on the support substrate while the solder member is separate from a portion of the wiring portion positioned in the vicinity of the bottom surface and the wiring portion is joined to the joining region.

Abstract: The present invention is directed to an ink composition for forming an organic semiconductor layer, wherein the ink composition comprises: —at least one p-type dopant comprising electron withdrawing groups; —at least one first auxiliary compound, wherein the first auxiliary compound is an aromatic nitrile compound, wherein the aromatic nitrile compound has about ?1 to about ?3 nitrile groups and a melting point of about <100° C., wherein the first auxiliary compound is different from the p-type dopant; and wherein the electron withdrawing groups are fluorine, chlorine, bromine and/or nitrile.

Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.

Abstract: The present disclosure relates to transparent P materials and their use in absorption layer(s), photoelectric conversion layer(s) and/or an organic image sensor and methods for their synthesis.

Abstract: This disclosure relates to semiconductor devices, and, more particularly, to a semiconductor structure that improves the switching speed of a switch for which the turn-off process depends on the recombination speed of charge carriers. The disclosure describes a semiconductor device formed on a semiconductor substrate that includes a power semiconductor switch having a drift region in the semiconductor substrate, an Extraction Plug in electrical contact with the drift region of the power semiconductor switch, and an extraction device electrically coupled to the Extraction Plug. The extraction device is structured to remove charge carriers from the drift region through the Extraction Plug when the extraction device is turned on. Methods are also described.

Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.

Abstract: Methods for integrating an image sensor and a light emitting diode (LED) leverage conformal depositions to achieve a single-sided, same height arrangement of contacts. In some embodiments, the method includes forming a plurality of cavities on a substrate where the plurality of cavities have a cavity profile and are configured to accept an emitter pixel structure or a sensor pixel structure, forming an emitter pixel structure in a cavity on the substrate where the emitter pixel structure is configured to have a plurality of exposed direct emitter contact areas on a same side and at a same height, and forming at least one sensor pixel structure in a cavity on the substrate where the sensor pixel structure is configured to have a plurality of exposed direct sensor contact areas on a same side and at a same height.

Abstract: An organic electroluminescent device is disclosed. The organic electroluminescent device achieves low driving voltage and high luminous efficiency as well as long lifespan by including an exciton confinement layer (ECL), in which a predetermined physical property is adjusted, in an area of an electron transporting area, including at least two layers, that is adjacent to an emissive layer.

Abstract: Disclosed is a pressure balancing clamp for a press-pack insulated gate bipolar transistor (IGBT) module. The pressure balancing clamp for a press-pack IGBT module includes a bracket, where the bracket is provided with two longitudinally arranged pressure equalizing plates in a sliding way; the pressure equalizing plates are connected through pressure sensors; the upper and lower ends inside the bracket are respectively connected with the pressure equalizing plates through hydraulic devices and a displacement compensation device; opposite surfaces of the two pressure equalizing plates are respectively provided with heat dissipation and confluence devices. The pressure sensors are in one-to-one correspondence with the hydraulic devices and are electrically connected. The hydraulic devices adjust the pressure according to the readings of the pressure sensors in corresponding directions, so that the pressure of the press-pack IGBT module is balanced.

Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.

Abstract: Disclosed are monolithically integrated three-dimensional (3D) DRAM array structures that include one-transistor, one-capacitor (1T1C) cells embedded at multiple device tiers of a layered substrate assembly. In some embodiments, vertical electrically conductive data-line and ground pillars extending through the substrate assembly provide the transistor source and ground voltages, and horizontal electrically conductive access lines at multiple device levels provide the transistor gate voltages. Process flows for fabricating the 3D DRAM arrays are also described.

Abstract: An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses.