Abstract: A semiconductor integrated circuit includes a first power line to which a first voltage is continuously applied, a second power line, a power switch cell connected to the first power line and configured to output a second voltage to the second power line according to a first signal, a logic circuit driven by the second voltage applied via the second power line, a first circuit driven by the second voltage applied via the second power line and configured to output a third voltage to logic circuit according to a second signal which is an inverted signal of the first signal, and a second circuit driven by the second voltage applied via the second power line and configured to output a fourth voltage to logic circuit according to a third signal which is an inverted signal of the second signal, the fourth voltage being lower than the third voltage.

Abstract: The present disclosure relates to a CMOS image sensor having a doped isolation structure separating a photodiode and a pixel device, and an associated method of formation. In some embodiments, the CMOS image sensor has a doped isolation structure separating a photodiode and a pixel device. The photodiode is arranged within the substrate away from a front-side of the substrate. A pixel device is disposed at the front-side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Comparing to previous image sensor designs, where an upper portion of the photodiode is commonly arranged at a top surface of a front-side of the substrate, now the photodiode is arranged away from the top surface and leaves more room for pixel devices. Thus, a larger pixel device can be arranged in the sensing pixel, and short channel effect and noise level can be improved.

Abstract: A transparent display panel includes a plurality of unit pixels. Each of the unit pixels includes a non-transparent region in which a first light-emitting element that generates and outputs first color light and a second light-emitting element that generates and outputs second color light are disposed and a transparent region in which a third light-emitting element that generates and outputs third color light is disposed.

Abstract: An organic light-emitting diode (OLED) structure includes an organic light-emitting diode having a first electrode, one or more layers of organic material disposed on at least a portion of the first electrode, and a second electrode disposed on at least a portion of the one or more layers of organic material. At least a portion of a tether extending from a periphery of the organic light-emitting diode. The organic light-emitting diodes can be printable organic light-emitting diode structures that are micro transfer printed over a display substrate to form a display.

Abstract: Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.

Abstract: A display device comprises a first substrate having a plurality of subpixels; a lower electrode disposed in each of the plurality of subpixels on the first substrate; a light emitting layer provided on the lower electrode; and an upper electrode disposed on the light emitting layer, wherein the light emitting layer includes a photoisomerized material.

Abstract: According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.

Abstract: The present invention relates to a light extraction substrate for an organic light emitting element and, more specifically, to a light extraction substrate for an organic light emitting element that can enhance the light extraction efficiency of the organic light emitting element by optimizing a stack structure that can maximize scattering efficiency, and an organic light emitting element comprising the same.

Abstract: A light-emitting device including a light-emitting semiconductor chip having a semiconductor layer sequence having at least one light-emitting semiconductor layer and a light-outcoupling surface, the light-emitting device further including a wavelength conversion layer arranged on the light-outcoupling surface, the wavelength conversion layer including quantum dots.

Abstract: A process for fabricating an optoelectronic device including an array of germanium-based photodiodes including the following steps: producing a stack of semiconductor layers, made from germanium; producing trenches; depositing a passivation intrinsic semiconductor layer, made from silicon; annealing, ensuring, for each photodiode, an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of a semiconductor portion, thus forming a peripheral zone of the semiconductor portion, made from silicon-germanium.

Abstract: A single photon avalanche diode (SPAT) image sensor is disclosed. The SPAT) image sensor include: a substrate of a first conductivity type, the substrate having a front surface and a back surface; a deep trench isolation (DTI) extending from the front surface toward the back surface of the substrate, the DTI having a first surface and a second surface opposite to the first surface, the first surface being level with the front surface of the substrate; an epitaxial layer of a second conductivity type opposite to the first conductivity type, the epitaxial layer surrounding sidewalls and the second surface of the DTI; and an implant region of the first conductivity type extending from the front surface to the back surface of the substrate. An associated method for fabricating the SPAD image sensor is also disclosed.

Abstract: An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

Abstract: A display device includes a substrate, a plurality of pixels above the substrate, each of the plurality of pixels including a first electrode, a light emitting layer above the first electrode, and a second electrode above the light emitting layer, a display region including the plurality of pixels, a first organic insulating layer located between the substrate and the light emitting layer, and a sealing layer above the second electrode and covering the plurality of pixels. The first organic insulating layer includes a first opening part surrounding the display region, the sealing layer has a first inorganic insulating layer, a second organic insulating layer and a second inorganic insulating layer, the first inorganic insulating layer and the second inorganic insulating layer cover the first opening part, a second opening part passing through the first inorganic insulating layer and the second inorganic insulating layer.

Abstract: Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.

Abstract: A semiconductor layout structure for a dynamic random access memory (DRAM) array comprises a plurality of active areas, an isolation structure and a plurality of word lines in a semiconductor substrate, where the isolation structure is situated among the plurality of active areas. Each of the plurality of active areas comprises a first segment extending in a first direction and a second segment extending in a second direction, one end of the first segment connected to an end of the second segment such that the active area presents a “V” shape. Two of the plurality of word lines intersect and traverse the first and second segments in each of the active areas respectively.

Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.

Abstract: A method of producing a light source device includes providing a light emitting device having a substrate including a base member that includes a bottom surface and a recess. The substrate further including a wiring portion in the recess. The method further including providing a support substrate having a support base member, a first wiring pattern on a top surface of the support base member and including a joining region, and an insulating region, and applying a solder member such that the solder member on the insulating region has a volume larger than that of the solder member on the joining region. The light emitting device is placed on the support substrate while the solder member is separate from a portion of the wiring portion positioned in the vicinity of the bottom surface and the wiring portion is joined to the joining region.

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

Abstract: Provided is a light-emitting element including a fluorescence-emitting material with high emission efficiency. The light-emitting element includes a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first organic compound, a second organic compound, and a guest material. The first organic compound has a function of emitting a thermally activated delayed fluorescence at room temperature. The guest material has a function of emitting fluorescence. A HOMO level of the first organic compound higher than or equal to a HOMO level of the second organic compound. A LUMO level of the first organic compound is lower than or equal to a LUMO level of the second organic compound.

Abstract: A die includes a semiconductor layer, an electrical contact on a first side of the semiconductor layer, a backside electrical contact layer on second side of the semiconductor layer. The die further includes a zinc layer over at least one of the electrical contact or the backside electrical contact layer of the die, and a conversion coating over the zinc layer. The conversion coating includes at least one of zirconium and vanadium. As part of an embedded die package including the die, at least a portion of the conversion coating may adjacent to an electrically insulating substrate of the embedded die package.