Abstract: A circuit breaker with enhanced convection and cooling comprises a housing having a first portion and a second portion. The circuit breaker further comprises one or more first orientation features formed onto the first portion of the housing. The circuit breaker further comprises one or more second orientation features formed onto the second portion of the housing such that the one or more first orientation features are different from the one or more second orientation features and the first portion of the housing is different than the second portion of the housing. The one or more first orientation features and the one or more second orientation features are assembled together to form air channels to allow air to go in and out while preventing a solid object from protruding and from touching inside components of the circuit breaker.

Abstract: Various embodiments of the present disclosure are directed towards a metal-insulator-metal (MIM) capacitor including a diffusion barrier layer. A bottom electrode overlies a substrate. A capacitor dielectric layer overlies the bottom electrode. A top electrode overlies the capacitor dielectric layer. The top electrode includes a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first and second top electrode layers.

Abstract: A method for manufacturing a MEMS structure is provided. The method includes providing a MEMS substrate having a first surface, forming a first buffer layer on the first surface of the MEMS substrate, and forming a first roughening layer on the first buffer layer. Also, a MEMS structure is provided. The MEMS structure includes a MEMS substrate, a first buffer layer, a first roughening layer, and a CMOS substrate. The MEMS substrate has a first surface and a pillar is on the first surface. The first buffer layer is on the first surface. The first roughening layer is on the first buffer layer. The CMOS substrate has a second surface and is bonded to the MEMS substrate via the pillar. Moreover, an air gap is between the first roughening layer and the second surface of the CMOS substrate.

Abstract: An organic electroluminescence device includes an anode, a cathode, a first emitting layer and a second emitting layer that are interposed between the anode and the cathode and are in a direct contact with each other, and a first electron transporting layer between the cathode and the first emitting layer and the second emitting layer being in a direct contact with each other. The first emitting layer contains a first compound represented by a formula (1) as a first host material, the first compound having at least one group represented by a formula (11). The second emitting layer contains a second compound represented by a formula (2) as a second host material. The first electron transporting layer contains a third compound represented by a formula (3).

Abstract: Provided is a compound of wherein: Y is O or S; X1 to X3 are each N or CH, and one or more of X1 to X3 is N; and Ar1 to Ar4 are the same as or different from each other, and each independently is an aryl group having 6 to 20 carbon atoms that is unsubstituted or substituted with nitrile or a heteroaryl group having 2 to 20 carbon atoms; or a tricyclic heteroaryl group having 2 to 20 carbon atoms that is unsubstituted or substituted with an aryl group having 6 to 20 carbon atoms, and an organic light emitting device including the same.

Abstract: The present specification relates to a heterocyclic compound represented by Chemical Formula 1, and an organic light emitting device comprising the same.

Abstract: A novel compound is provided. A light-emitting element with high emission efficiency and a long lifetime is provided. The compound is an organic compound that includes a benzofuro[3,2-d]pyrimidine or benzothieno[3,2-d]pyrimidine skeleton (General Formula (G0)). The 2-position of the benzofuro[3,2-d]pyrimidine or benzothieno[3,2-d]pyrimidine skeleton has a substituent and the 6- to 9-positions of the skeleton have at least one substituent. Any one of the substituents bonded to the 6- to 9-positions is bonded to the benzofuro[3,2-d]pyrimidine or benzothieno[3,2-d]pyrimidine skeleton via a phenylene group. A light-emitting element including the compound is provided.

Abstract: In a ROM cell using a vertical nanowire (VNW) FET, the gate of the VNW FET is connected with a word line (WL), the bottom thereof is connected with a bit line (BL), and the top thereof is selectively connected with a ground potential line. The bottom of the VNW FET of the ROM cell is connected to the bit line (BL) irrespective of the data stored in the ROM cell.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a well, an oxidation layer, a gate electrode and a shared source/drain electrode. The substrate has a first surface and a second surface opposite to each other. The well is formed in the substrate. The substrate and the well have a first conductivity type and a second conductivity type respectively. The oxidation layer is formed in the well. The gate electrode is formed above the first surface and has a first opening. The shared source/drain electrode is formed near the first surface in the oxidation layer and exposed from the first opening. The shared source/drain electrode has the first conductivity type.

Abstract: Aspects of the disclosure provide a semiconductor apparatus including a first stack of transistors and a second stack of transistors. The first stack includes a first transistor and a second transistor stacked on the first transistor along a Z direction perpendicular to a substrate plane. The second stack includes a third transistor and a fourth transistor stacked on the third transistor along the Z direction. The semiconductor apparatus includes a first routing track and a second routing track electrically isolated from the first routing track. The first and second routing tracks extend in an X direction parallel to the substrate plane. A first and fourth conductive trace conductively couple a first gate of the first transistor and a fourth gate of the fourth transistor to the first routing track, respectively. A first terminal structure conductively couples four source/drain terminals of the first, second, third and fourth transistors, respectively.

Abstract: A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

Abstract: A front emission type display device is provided. In the display device, light generated by a light-emitting element which is disposed on a first substrate can be emitted to the outside through a color filter and a second substrate, so that an image can be realized on an outer surface of the second substrate. In the display device, a space between a first device passivation layer on the light-emitting element, and a second device passivation layer on the second substrate can be filled by the color filter and a pixel defining pattern disposed on a side surface of the color filter. Thus, in the display device, the distortion of the first substrate and the second substrate can be prevented or reduced.

Abstract: A semiconductor substrate has a front face and a back face. A first contact and a second contact, spaced apart from each other, are located on the front face. An electrically conductive wafer is located on the back face. A detection circuit is configured to detect a thinning of the substrate from the back face. The detection circuit including a measurement circuit that takes a measurement of a resistive value of the substrate between said at least one first contact, said at least one second contact and said electrically conductive wafer. Thinning is detected in response to the measured resistive value.

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

Abstract: The present specification relates to a heterocyclic compound represented by Chemical Formula 1, and an organic light emitting device comprising the same.

Abstract: A multi-color light emitting pixel unit includes a substrate, and a light emitting transistor formed on the substrate. The light emitting transistor includes a bottom conductive layer formed on the substrate and a top conductive layer formed over the bottom conductive layer, an upper light emitting layer formed between the top conductive layer and the bottom conductive layer, at least one lower light emitting layer formed between the upper light emitting layer and the bottom conductive layer, and an electrical connector electrically connecting the at least one lower light emitting layer and the bottom conductive layer.

Abstract: A semiconductor chip may have at least one p-channel field effect transistor (FET), at least one n-channel FET, a first and a second power supply terminal, wherein the at least one n-channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p-channel FET and the at least one p-channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel FET, a precharge circuit to precharge the circuit to a first state, and a detection circuit configured to output an alarm signal if the circuit enters a second state.

Abstract: A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

Abstract: The scanning antenna includes a TFT substrate, a slot substrate including a slot electrode, a liquid crystal layer provided between the TFT substrate and the slot substrate, and a reflective conductive plate. Each of the plurality of antenna units includes a TFT, a patch electrode electrically connected to the drain of the TFT, a slot formed in the slot electrode corresponding to the patch electrode, and a first region in which the patch electrode and the slot electrode overlap each other when viewed from the normal direction of the first dielectric substrate. A distance in the normal direction of the first dielectric substrate between the patch electrode and the slot electrode of the plurality of second antenna units is smaller than a distance in the normal direction of the first dielectric substrate between the patch electrode and the slot electrode of the plurality of first antenna units.

Abstract: A semiconductor integrated circuit includes a first power line to which a first voltage is continuously applied, a second power line, a power switch cell connected to the first power line and configured to output a second voltage to the second power line according to a first signal, a logic circuit driven by the second voltage applied via the second power line, a first circuit driven by the second voltage applied via the second power line and configured to output a third voltage to logic circuit according to a second signal which is an inverted signal of the first signal, and a second circuit driven by the second voltage applied via the second power line and configured to output a fourth voltage to logic circuit according to a third signal which is an inverted signal of the second signal, the fourth voltage being lower than the third voltage.