Abstract: Systems and methods for managing performance and quality of service (QoS) with multiple namespace resource allocation. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. NVMe may support the use of namespaces. Namespace configuration may be modified to include performance criteria specific to each namespace. The memory device may then receive commands directed to specific namespaces an apply memory device resources to commands in each namespace queue such that QoS may be applied to control execution of commands such that commands in each namespace receive resources based on host selected performance parameters for each namespace.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request for data. A number of storage devices of a plurality of storage devices in a Mapped RAID group that will be used to process the I/O request may be determined. It may be determined that each storage device of the number of storage devices in the Mapped RAID group that will be used to process the I/O request lacks a respective threshold number of credits to process the I/O request. It may be determined whether a cache associated with the Mapped RAID group allows a user I/O queue. If the cache allows the user I/O queue, a user I/O may be placed in the user I/O queue. If the cache does not allow the user I/O queue, the I/O request may be failed.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, one or more drives added to an extent pool of storage devices. An empty Mapped RAID group may be generated. A plurality of extents in the extent pool may be shuffled. A RAID extent may be mapped to the empty Mapped RAID group, wherein the RAID extent is mapped to the empty Mapped RAID group while shuffling the plurality of extents in the extent pool.

Abstract: Facilitating processing in a computing environment. A request to access a cache of the computing environment is obtained from a transaction executing on a processor of the computing environment. Based on obtaining the request, a determination is made as to whether a tracking set to be used to track cache accesses is to be updated. The tracking set includes a read set to track read accesses of at least a selected portion of the cache and a write set to track write accesses of at least the selected portion of the cache. The tracking set is assigned to the transaction, and another transaction to access the cache has another tracking set assigned thereto. The tracking set assigned to the transaction is updated based on the determining indicating the tracking set is to be updated.

Abstract: A technique for managing storage space in a data storage system generates liability values on a per-family basis, with each family including files in the file system that are related to one another by snapping. Each family thus groups together files in the file system that generally share at least some blocks among one another based on snapshot activities. Distinct files that do not share blocks based on snapping are provided in separate families. The technique further generates worst-case storage liability of a version family by differentiating between writable data objects and read-only data objects, thus allowing administrators to provide spare storage and/or prepare for increases in storage requirements as writable data objects grow and differentiate.

Abstract: A method and an apparatus for generating a signature representative of the content of a region of an array of data in a data processing system, where the region of the array of data comprising plural data positions, and each data position having an associated data value or values. A data value or values for a data position of the region of the data array is/are generated. The data value or values for the data position of the region of the data array is/are written to storage that stores the region of the data array as it is being generated. A signature representative of the content of the region of the data array is generated in parallel with the data value or values for the data position of the region of the data array being written to the storage.

Abstract: A solid-state drive includes a flash memory device, a power loss protection circuit, a dynamic random access memory (RAM) coupled to the power loss protection circuit, and a controller configured to direct I/O requests to either the flash memory drive or the RAM. Because the controller can direct I/O request to the RAM, the RAM is revealed as a separate mass storage device to a host. Consequently, the RAM provides additional and significantly higher performance storage capacity to the solid-state drive.

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

Abstract: A firmware inventory system for efficient firmware inventory of storage devices in an information handling system may include a first storage subsystem. The first storage subsystem may include a first set of storage devices, a first inventory information table, and a first expander. The expander may include a first memory, a first processor, and a first virtual SEP device stored in the first memory and executable by the first processor. The first virtual SEP device may, when a device change event is received from a first storage device of the first set of storage devices, send a device information request to the first storage device, receive a device information response including device information of the first storage device from the first storage device in response to the device information request and update the first inventory information table with the device information of the first storage device.

Abstract: Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

Abstract: A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.

Abstract: A computer-implemented method according to one embodiment includes receiving a first command to inhibit one or more tracks within a volume of a storage system, in response to the first command, identifying the one or more tracks within the volume of the storage system, utilizing the first command or a previous command, and inhibiting the one or more tracks within the volume of the storage system, receiving a second command to copy data to the one or more tracks within the volume of the storage system, identifying the one or more tracks within the volume of the storage system as inhibited, and rejecting the second command, in response to the identifying.

Abstract: A data storage system has a processor that performs deduplication operations on input/output data, and determines a space savings obtained for each one of the deduplication operations. The processor also determines a maximum space savings based on the space savings obtained for each one of the deduplication operations, and determines an optimal data block size based on the maximum space savings.

Abstract: In some cases, processor graphics with a slower local memory can compensate by using another memory in place of the lowest level or L3 cache. For example, in some processors, there is a large register space that can be used for the local memory function by allocating the local memory within those registers. Also, since the registers do not operate with barriers, barriers can be simulated by letting one execution unit thread execute more SIMD instructions. For example, one execution thread may simulate a whole work-group in the OpenCL API.

Abstract: A method for accessing an entry in a translation lookaside buffer and a processing chip are provided. In the method, the entry includes at least one combination entry, and the combination entry includes a virtual huge page number, a bit vector field, and a physical huge page number. The physical huge page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages. One entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses. In this way, a delay in program processing can be reduced, and processing efficiency of the processing chip can be improved.

Abstract: A system and method improve the performance of non-volatile memory storage by facilitating direct memory access (DMA) transfers between a remote host and a non-volatile memory based storage system, such as a flash memory based data storage device (e.g., a solid state drive (SSD)). In conjunction with reading from and writing to non-volatile memory storage, a memory buffer on the non-volatile memory system is allocated, and a read or write command is translated to point to the allocated buffer. Thereafter, read and write operations may be performed through a controller, such as a non volatile memory express (NVMe) controller, using remote direct memory access (RDMA) transfers, thus bypassing time consuming processor steps of buffering data to main memory and allowing bi-directional throughput to reach network and SSD speeds.

Abstract: In one embodiment, an apparatus comprises a plurality of memory partitions, each memory partition comprising an array of 3D crosspoint memory, and a storage device controller comprising a memory comprising memory cells to store addresses of replacement memory partitions and addresses of unusable memory partitions and a partition address translation engine coupled to the memory, the partition address translation engine comprising logic to determine whether to redirect a memory access command received from a host computing device to a replacement memory partition based on the contents of the memory.

Abstract: In various implementations, provided are systems and methods for an integrated circuit implementing a processor that can include a rate limiting circuit that attempts to fairly distribute processor memory bandwidth between transaction generators in the processor. The rate limiting circuit can maintain a count of tokens for each transaction generator, where a transaction generator can only transmit a transaction when the transaction generator has enough tokens to do so. Each transaction generator can send a request to the rate limiting circuit when the transaction generator wants to transmit a transaction. The rate limiting circuit can then check whether the transaction generator has sufficient tokens to transmit the transaction. When the transaction generator has enough tokens, the rate limiting circuit will allow the transaction to enter the interconnect. When the transaction generator does not have enough tokens, the rate limiting circuit will not allow the transaction to enter the interconnect.

Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a semiconductor memory device for including a plurality of semiconductor memories, and operating in response to a plurality of internal commands received thereto; and a controller for generating and queuing the plurality of internal commands in response to a plurality of commands received from a host, and generating and storing a master bitmap including information on unperformed operations that are not performed in the semiconductor memory device for internal commands among the plurality of queued internal commands. The controller generates a flush bitmap corresponding to a flush command, using a current master bitmap, when the flush command is received from the host, and clears the flush bitmap if the semiconductor memory device completes the unperformed operations.

Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for determining that an object implicated in an executing application is to be allocated to memory in an in-memory system, determining a type of the object, and allocating the object to one of a first size of virtual memory page and a second size of virtual memory page of an operating system based on the type of the object.