Abstract: A control apparatus configured to determine a first value indicating a resource amount of a first storage apparatus, determine, respectively for a plurality of logical volumes included in the first storage apparatus, a load of the first storage apparatus due to access from an information processing apparatus, determine a priority of the plurality of logical volumes, respectively, for a process of data migration from a second storage apparatus to the first storage apparatus, determine a second value indicating a resource amount of the first storage apparatus which is used in the access from the information processing apparatus to the first storage apparatus, calculate, as a migration resource amount of the first storage apparatus, a value by subtracting the second value from the first value, allocate the migration resource amount to the plurality of logical volumes based on the priority respectively determined for the plurality of logical volumes.

Abstract: Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein each of the plurality of nested translation requests requires at least one congruence class lock; detecting, using a congruence class scoreboard, a collision of the plurality of nested translation requests based on the required congruence class locks; quiescing, in response to detecting the collision of the plurality of nested translation requests, a translation pipeline in the MMU including switching operation of the translation pipeline from a multi-thread mode to a single-thread mode and marking a first subset of the plurality of nested translation requests as high-priority nested translation requests; and servicing the high-priority nested translation requests through the translation pipeline in the single-thread mode.

Abstract: A method for protecting a computer includes identifying a first pointer in a data structure used by a computer program indicating a first memory address to be accessed, using the pointer, in order to invoke a functionality of the computer. The identified first pointer is replaced with a second pointer indicating a second memory address, different from the first memory address. A security program module traps attempts to access the second memory address during execution of the computer program so as to foil unauthorized access to the functionality of the computer.

Abstract: Data storage apparatus comprises detection circuitry configured to detect a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detection circuitry comprising: a comparator configured to compare, as a first comparison, a first subset of bits of the reference memory address with a combination of the corresponding first subset of bits of the base address and the corresponding first subset of bits of the address offset; the comparator being configured to compare, as a second comparison, a second, different subset of bits of the reference memory address with the corresponding second subset of bits of the base address; a detector configured to detect the match between the reference memory address and the test address when both of the first comparison and the second comparison detect a respective match; and control circuitry configured to control operation of the data storage apparatus in dependen

Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.

Abstract: A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual address is computed based on the delta value and the first virtual address. Data associated with the second virtual address is then prefetched from a main memory to the data cache prior to a second load instruction specifying the second virtual address missing in the data cache.

Abstract: In some examples, a storage device includes a first non-volatile memory array configured to store data from a host device and the storage device and a second non-volatile memory array configured to store data from the storage device, wherein the second non-volatile memory array is separate from the first non-volatile memory array. The storage device also includes a controller configured to store a virtual-to-physical mapping table to the first non-volatile memory array and store a portion of the virtual-to-physical mapping table to the second non-volatile memory array.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device operates based on a store data request from a requesting entity to dispersed error encode a data segment associated with a data object to generate a set of encoded data slices (EDSs). The computing device selects a write threshold number of EDSs based on a desired consistency level indicator and issues a write request to storage unit(s) (SU(s)). The computing device receives write response(s) from the SU(s) and, based on write response(s) received from the at least some of the SU(s), provides a store data response to the requesting entity.

Abstract: A method is described for enabling inter-process communication between a first application and a second application, the first application running within a first virtual machine (VM) in a host and the second application running within a second VM in the host, The method includes receiving a request to attach a shared region of memory to a memory allocation, identifying a list of one or more physical memory pages defining the shared region that corresponds to the handle, and mapping guest memory pages corresponding to the allocation to the physical memory pages. The request may be received by a framework from the second application and includes a handle that uniquely identifies the shared region of memory as well as an identification of at least one guest memory page corresponding to the memory allocation.

Abstract: Systems and methods for pre-fetching data based on memory usage patterns. An example method comprises: receiving a first memory access request identifying a first memory block; receiving a second memory access request identifying a second memory block; update a memory access tracking data structure by incrementing a sequence counter corresponding to a memory access sequence that references the first memory block and the second memory block; receive a third memory access request identifying a third memory block; identifying, based on the memory access tracking data structure, a sequence counter having a maximal value among sequence counters associated with memory access sequences that reference the third memory block; and pre-fetching a fourth memory block corresponding to the identified sequence counter.

Abstract: Methods for use in a dispersed storage network (DSN) to coordinate data slice arrival times. In various examples, a DSN computing device receives a store data request, the store data request including a data object. A set of storage units associated with the store data request is identified, and the data object is dispersed storage error encoded to produce a plurality of sets of encoded data slices. One or more sets of write slice requests that include one or more sets of encoded data slices are also generated for reception by storage units of the set of storage units. For each set of write slice requests, a transmission schedule is determined for each write slice request such that the set of write slice requests arrives at corresponding storage units at substantially the same time frame. Each of the write slice requests is then transmitted in accordance with the transmission schedule.

Abstract: A technique that reduces the startup time of a processing system authenticates a proxy for an image stored in tracked memory instead of authenticating the image stored in the tracked memory. A controller generates an alteration log authentication code based on an alteration log that is updated prior to programming the image stored in tracked memory. The controller records an alteration log authentication code in secure memory. The alteration log is indirectly related to a most recent image stored in the tracked memory. Authentication of the image of the alteration log is used as a proxy for authentication of the image stored in tracked memory, which is performed only when the tracked memory is modified. Use of the contents of the alteration log as a proxy for the contents of tracked memory accelerates the startup time of the system.

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

Abstract: A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.

Abstract: Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.

Abstract: According to one embodiment, a memory device includes a first memory, a control circuit controlling the first memory, and a second memory storing a second program. The second program manages management information associated with the first memory, sends the management information conforming to a specific interface to a first program if a command conforming to the specific interface is an output command to output the management information. The second program receives first information conforming to the specific interface and issued by the first program, translates the first information into second information corresponding to the second program, translates the second information into third information corresponding to the control circuit, and executes processing for the first memory in accordance with the third information.

Abstract: A prefetch request having a priority assigned thereto is obtained, based on executing a prefetch instruction included within a program. Based on obtaining the prefetch request, a determination is made as to whether the prefetch request may be placed on a prefetch queue. This determination includes determining whether the prefetch queue is full; checking, based on determining the prefetch queue is full, whether the priority of the prefetch request is considered a high priority; determining, based on the checking indicating the priority of the prefetch request is considered a high priority, whether another prefetch request on the prefetch queue may be removed; removing the other prefetch request from the prefetch queue, based on determining the other prefetch request may be removed; and adding the prefetch request to the prefetch queue, based on removing the other prefetch request.

Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

Abstract: A data storage system creates, maintains and utilizes logical storage structures including (1) a pool of device extents on user devices, organized into data portions of mapped RAID groups each having a data portion and a RAID group metadata element having (i) a basic portion and (ii) a mapping portion mapping each set of device extents to logical RAID extents per RAID type, (2) a pool logical device (e.g., an internal mapped RAID) in the pool, storing the mapping portions of the metadata elements of the mapped RAID group, and (3) a system logical device on separate system devices, storing (i) the basic portions of the metadata elements of the RAID groups, and (ii) a pool metadata element including a pool mapping portion for the pool logical device.

Abstract: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load balancing within the system and improve overall system performance as further described herein. Another aspect of the invention may involve performing certain predictive analyses on system operation to reveal trends and tendencies within the system. Such information may be used as the basis for potentially migrating components from one storage operation cell to another to improve system performance and reduce or eliminate resource exhaustion or congestion conditions.