Abstract: In an organic EL device, the light emission efficiency by a TADF mechanism is to be improved with an emissive layer structure that can be easily formed. An OLED has at least an emissive layer between an upper electrode and a lower electrode. The emissive layer includes: a host layer including a host material; an assistant dopant layer which is a layer adjacent to the host layer and where an assistant dopant made of a thermally activated delayed fluorescence material and the host material are intermingled within a plane; and a light-emitting dopant layer which is a layer adjacent to the assistant dopant layer and where a light-emitting dopant made of a fluorescent material emitting light by being excited by the assistant dopant and the host material are intermingled within a plane.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner. The first conducting layers are connected to the memory cells and are arrayed in a laminating direction. Stepped wiring portion includes a plurality of second conducting layers. The plurality of second conducting layers connect the first conducting layers and external circuits. At least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side. Other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.

Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

Abstract: Discussed are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device according to an embodiment includes a substrate including an active area and a pad area, a thin film transistor (TFT) in the active area of the substrate, an anode electrode on the TFT, an organic emission layer on the anode electrode, a cathode electrode on the organic emission layer, an auxiliary electrode connected to the cathode electrode and disposed on the same layer as the anode electrode, a signal pad in the pad area of the substrate, and a pad electrode connected to the signal pad to cover a top of the signal pad for preventing the top of the signal pad from being corroded. The TFT includes a gate electrode. The signal pad is disposed on the same layer as the gate electrode.

Abstract: A display device includes a substrate and pixels arranged on the substrate in a matrix form. The substrate includes a display area in which the pixels are arranged and a non-display area disposed adjacent to a side of the display area. Each pixel includes a cover layer that extends in a row direction that includes a sidewall portion connected to the substrate and a cover portion spaced apart from the substrate and connected to the sidewall portion to define a tunnel-shaped cavity on the substrate. A width of the sidewall portion between adjacent pixels is less than a width of the sidewall portion disposed at an outermost position, and the cover layer seals one side of the tunnel-shaped cavity in the pixels arranged in a first row and a last row.

Abstract: A fully depleted field effect transistor (FET) and an anti-fuse structure are provided on a same chip. The fully depleted FET and the anti-fuse structure share a same high dielectric (k) constant dielectric material. The anti-fuse structure contains a faceted epitaxial doped semiconductor material as a bottom electrode, a high k dielectric material portion, and a gate electrode material portion as a top electrode. The sharp corners of the faceted epitaxial doped semiconductor material cause electric field concentration, which aid in the reduction of the breakdown voltage of the anti-fuse structure.

Abstract: A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is TS1 and the thickness of the second region is TG1, TS1?TG1.

Abstract: A method carried out on a computer system for ordering and executing expedited production options. A user may submit a request for manufacturing a product defined by a 3D computer model. Systems described herein may then verify that the request is subject to an expedited production option and parse the 3D computer model to identify the processes required to manufacture the product. The product may then be manufactured with an expedited lead time that may vary as a function of the processes in question and the nature of the applicable expedited production option.

Abstract: A semiconductor device is reduced in power consumption, the semiconductor device including a solid-state imaging device that includes pixels each having a plurality of light receiving elements. A pixel having first and second photodiodes is provided with a first transfer transistor that transfers charge in the first photodiode to a floating diffusion capacitance section, and a second transfer transistor that combines charge in the first photodiode and charge in the second photodiode, and transfers the combined charge to the floating diffusion capacitance section. Consequently, the semiconductor device is reduced in power required for activation of each transfer transistor in operation such as imaging with the solid-state imaging device.

Abstract: An organic light emitting display device includes: a first light emitting unit including a first light emitting layer; and a second light emitting unit on the first light emitting unit including a second light emitting layer. The first light emitting layer includes at least one dopant and at least two hosts. The at least two hosts are different from each other in electron mobility and hole mobility.

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.

Abstract: The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics.

Abstract: A semiconductor structure that has adjacent transistors that share a common source/drain semiconductor structure. At least one of the adjacent transistors comprising: a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.

Abstract: A MEMS microphone with reduced parasitic capacitance is provided. A microphone includes a protection film covering a rim-sided area of the backplate.

Abstract: A COA (Color filter On Array) substrate and a manufacturing method using the same are disclosed. The method includes: forming a first metal layer, a gate insulation layer, a color resist layer, an active layer, a second metal layer, a passivation layer, a via hole, and a transparent conductive layer in order. The via hole is used for connecting to the transparent conductive layer with the second metal layer. The transparent conductive layer is formed on the passivation layer. A gate electrode is formed by pattering the first metal layer. A drain electrode and a source electrode are formed by pattering the second metal layer. In the present invention, the color resist layer is made before the second metal layer.

Abstract: A light emitting device includes a substrate including gallium nitride, and a semiconductor layer disposed on the substrate, the semiconductor layer including an n-type nitride semiconductor layer, an active layer disposed on the n-type nitride semiconductor layer, and a p-type nitride semiconductor layer disposed on the active layer, in which an angle defined between a crystal growth plane of the substrate and an m-plane thereof is in a range of 3.5° to 6.

Abstract: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge wiring (28) is formed between the LEDs (1) and between the LEDs (1) and electrodes (32). The LED arrays are arranged zigzag to form a plurality of LEDs (1) to produce a high drive voltage and a small drive current. Two LED arrays are connected in inverse parallel, and therefore an AC power supply can be used as the power supply.

Abstract: Provided is a method for manufacturing a highly reliable display device.

Abstract: A method for exposing an electrode terminal covered with an organic film in a light-emitting device without damaging the electrode terminal is provided. In a region of the electrode terminal to which electric power from an external power supply or an external signal is input, an island-shaped organic compound-containing layer is formed and the organic film is formed thereover. The organic film is removed by utilizing low adhesion of an interface between the organic compound-containing layer and the electrode terminal, whereby the electrode terminal can be exposed without damage to the electrode terminal.

Abstract: An organic light-emitting display device is provided. The device can include a display area having an organic light-emitting element on a lower substrate; a bezel area surrounding the display area; a transparent encapsulation unit having first and second encapsulation layers, and a first particle cover; and a first buffer layer. The first encapsulation layer can cover the display area and the bezel area. The first particle cover layer can cover the display area and a portion of the bezel area adjacent to the display area. The first buffer layer, apart from the first particle cover layer, can cover another portion of the bezel area. The second encapsulation layer, which covers the first particle cover layer and the first buffer layer, contacts the first encapsulation layer at a contact surface between the first particle cover layer and the first buffer layer.