Abstract: An organic light emitting diode display device includes: a substrate; a first antireflection line formed on the substrate and including a first metallic layer and a first inorganic layer stacked sequentially; a gate line formed on the first antireflection line; a gate insulation layer formed on the substrate and the gate line; a second antireflection line formed on the gate insulation layer and including a second metallic layer and a second inorganic layer stacked sequentially; a data line formed on the second antireflection line; and wherein the first inorganic layer connects the first metallic layer and the gate line electrically and the second inorganic layer connects the second metallic layer and the data line.

Abstract: A flexible display device is disclosed. In one aspect, the device includes a display substrate including a display area and a non-display area surrounding the display area, wherein the display area includes an emission element layer. An inorganic layer is formed over the display substrate in the display area and the non-display area, and a thin film encapsulation layer is formed over the inorganic layer and covering at least a portion of the inorganic layer. A plurality of dummy patterns are formed over the display substrate and the inorganic layer. The dummy patterns include a plurality of first dummy patterns formed in the non-display area of the display substrate not overlapping the inorganic layer, and a plurality of second dummy patterns formed in the non-display area of the of the display substrate overlapping the inorganic layer.

Abstract: A semiconductor structure having an electrical contact that is connected to source/drain structures of two different transistors. The semiconductor structure has a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.

Abstract: An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device.

Abstract: The present disclosure provides a substrate-sealing method, frit and an electron device, and relates to the field of sensitive electronic components sealing technology. The method includes: coating glass cement on a first glass substrate within a sealing area, the glass cement including carbon nanotubes; pressing the first glass substrate and a second glass substrate together, and melting and sintering the glass cement between the first glass substrate and the second glass substrate at the sealing area by irradiating the sealing area with a laser.

Abstract: A display device includes light emitting elements that are arranged in a two-dimensional matrix, in which the light emitting elements include a drive circuit which is provided on a substrate, a first insulating layer which covers the drive circuit and the substrate, a light emitting portion in which a first electrode, an organic layer having a light emitting layer, and a second electrode are laminated, and a second insulating layer which covers the first electrode.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

Abstract: The present invention discloses a display panel, a manufacturing method thereof and a display device. The display panel comprises a first substrate divided into a display area and a non-display area surrounding the display area, a plurality of sub-pixel units are provided on a part of the first substrate corresponding to the display area, a photo spacer is provided between two adjacent sub-pixel units and comprises a base and a plurality of protruding structures provided on the base, and the base is made from material including In+ ions which are replaceable with H+ ions. For the display panel, the photo spacers are manufactured using Haze phenomenon generated by contacting ITO thin film with ionized H2, so as to provide support between the encapsulation substrate and the evaporated substrate encapsulated by frit seal and effectively protect the OLED devices from damage, and therefore, the display panel has better performance.

Abstract: The double-face display panel comprises a plurality of pixel units arranged in an array mode, and the pixel unit comprises an anode, a cathode, an organic material functional layer arranged between the anode and the cathode and at least one thin film transistor, wherein the anode comprises a transmission anode and a reflection anode, the cathode comprises a transmission cathode and a reflection cathode, the transmission anode at least corresponds to the reflection cathode, the transmission cathode at least corresponds to the reflection anode, and the reflection anode and the reflection cathode are arranged in a staggered mode; the transmission anode is electrically connected with a drain electrode of the thin film transistor, and the reflection anode is electrically connected with the drain electrode of the thin film transistor.

Abstract: A method for fabricating a high-voltage field-effect transistor includes forming a body region, a source region, and a drain region in a semiconductor substrate. The drain region is separated from the source region by the body region. Forming the drain region includes forming an oxide layer on a surface of the semiconductor substrate over the drain region and performing a plurality of ion implantation operations through the oxide layer while tilting the semiconductor substrate such that ion beams impinge on the oxide layer at an angle that is offset from perpendicular. The plurality of ion implantation operations form a corresponding plurality of separate implanted layers within the drain region. Each of the implanted layers is formed at a different depth within the drain region.

Abstract: Technical solutions are described for forming a semiconductor device for a crosspoint array that implements a pre-programmed neural network. An example method includes sequentially depositing a semiconducting layer, a top insulating layer, and a shunting layer onto a base insulating layer. The method further includes etching selective portions of the top insulating layer corresponding to resistance values associated with weights of the crossbar that implements the neural network.

Abstract: According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device.

Abstract: An organic light emitting diode display includes a scan line, a data line, and a driving voltage line connected to a pixel. The pixel includes a switching transistor connected to the scan line and the data line, a driving transistor connected to the switching transistor, and a compensation transistor to compensate a threshold voltage of the driving transistor. The pixel also includes a first data connector to connect the compensation transistor to the driving transistor, a first storage electrode corresponding to the driving gate electrode and connected to the driving voltage line, and a second storage electrode overlapping a first storage electrode. An extended portion of the second storage electrode is in an overlapped portion between the first data connector and the scan line.

Abstract: A manufacturing method of a sensing integrated circuit including the following acts. A plurality of transistors are formed. At least one dielectric layer is formed on or above the transistors. A plurality of connecting structures are formed in the dielectric layer. The connecting structures are respectively and electrically connected to the transistors. A plurality of separated conductive wells are respectively formed in electrical contact with the connecting structures.

Abstract: An organic electroluminescence multicolor light-emitting apparatus including: a substrate; and a first light-emitting device and a second light-emitting device being arranged in parallel relative to the surface of the substrate; wherein the first light-emitting device includes, between an anode and a cathode, a first organic layer, a second organic layer and a third organic layer in this sequence from the anode side in a direction perpendicular to the surface of the substrate, the second light-emitting device includes, between an anode and a cathode, a second organic layer and a third organic layer in this sequence from the anode side in a direction perpendicular to the surface of the substrate, the first organic layer includes a first emitting dopant, the third organic layer includes a second emitting dopant, and the second organic layers independently comprise any one of compounds represented by the following formulas (1) to (6).

Abstract: A fully depleted field effect transistor (FET) and an anti-fuse structure are provided on a same chip. The fully depleted FET and the anti-fuse structure share a same high dielectric (k) constant dielectric material. The anti-fuse structure contains a faceted epitaxial doped semiconductor material as a bottom electrode, a high k dielectric material portion, and a gate electrode material portion as a top electrode. The sharp corners of the faceted epitaxial doped semiconductor material cause electric field concentration, which aid in the reduction of the breakdown voltage of the anti-fuse structure.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and an active pattern formed over the substrate and including first to fourth regions. A gate insulation layer is formed over the active pattern and the substrate, and a first gate electrode is formed over the gate insulation layer and partially overlapping the active pattern. The first gate electrode, the first region and the second region define a first transistor. A second gate electrode is formed on the same layer as the first gate electrode. The second gate electrode, the third region and the fourth region define a second transistor, and the second gate electrode, the second region and the fourth region define a third transistor. A first insulating interlayer is formed over the first gate electrode, the second gate electrode, and the gate insulation layer.

Abstract: The present disclosure provides an OLED display panel, which sequentially includes: a first light emitting layer covering at least two adjacent sub-pixels including the first sub-pixel; a charge blocking layer covering the second sub-pixel and the third sub-pixel; a second light emitting layer covering the first sub-pixel and the second sub-pixel; a third light emitting layer covering at least two adjacent sub-pixels including the third sub-pixel. LUMO energy levels of a main material of the charge blocking layer, a main light emitting material of the third light emitting layer, a main light emitting material of the second light emitting layer and a main light emitting material of the first light emitting layer are sequentially decreased; or, HOMO energy levels of the main light emitting materials of the first light emitting layer, the second light emitting layer, the third light emitting layer and the charge blocking layer are sequentially decreased.