Abstract: A differential voltage comparator for driving a digital logic gate includes a differential amplifier stage for receiving V.sub.IN and NOT V.sub.IN input signals, a left voltage level shifter for shifting the output of the left side of the differential amplifier by a predetermined voltage, and a differential current source for the differential amplifier biased on one side by the left voltage level shifter and on its other side by a reference voltage. An output voltage level shifter shifts down the output voltage from the differential comparator by a predetermined amount; and applied the shifted voltage to an output terminal. Transistors in the differential current source are matched to transistors in the digital logic gate being driven for providing an offset in the differential current source; the latter along with equating the shift down voltage of the left voltage level shifter to the sum of the reference voltage and output shift down voltage, ensures that when V.sub.IN is equal to NOT V.sub.

Abstract: A linear interpolator comprising an amplifier, an integrator for integrating an output of the amplifier, a feedback circuit connected between the amplifier and the integrator for bootstrapping an input voltage of the amplifier by an output voltage from the integrator, and a switch for periodically supplying a staircase input signal to the amplifier. A linearly interpolated output is derived from the integrator. The discrete input signal changing stepwise can be linearly interpolated with high accuracy.

Abstract: An integrated circuit is provided which uses a single drive signal for turning a PNP switching transistor "on" and "off." An NPN transistor provides reverse drive current to the PNP transistor's base. When the drive signal is present, the PNP switching transistor is turned "on" and is driven into saturation. The drive signal during this period also charges an integrated capacitor coupled to the base of the NPN transistor. The drive signal then is removed to turn the PNP transistor "off." Removal of the drive signal also causes the voltage developed across the capacitor to drive the base of the NPN transistor. This, in turn, causes the NPN transistor to drive the base of the PNP transistor with a reverse drive current, thus speeding up the switching of the PNP transistor from the conducting state to the non-conducting state.

Abstract: A phase lock loop for a digital input signal has a phase detector, a loop filter, a digital voltage controlled oscillator (VCO), an initial phase difference calculator, a center frequency difference calculator and an input buffer memory. In an initial training mode prepared in the PLL operation, an optimum initial phase and an optimum center frequency of the VCO to complete a lock-in state is searched for the input signal stored in the buffer memmory. By estimating the initial phase difference and the center frequency difference between the input signal and the VCO output with repetative kick-offs in calculators, optimum values mentioned above are obtained.

Abstract: A current compensation circuit for a comparator includes a pair of switching transistors which supply input bias current to their corresponding comparator input transistors, a pair of current to voltage conversion means which use collector current from the comparator input transistors to turn on and off the appropriate switching transistor when its corresponding comparator input transistor is on, a transistor to generate a negative replica of the input bias current flowing in the comparator input, and a current mirror which is programmed by the replica of the uncompensated input bias current to produce a compensated input bias current to the switching transistors.

Abstract: A Digital Phase Comparator has a simplified logic circuit in which Nand Circuits provide UP and DOWN signals containing phase information about E and F signals.

Abstract: A sawtooth generator for an oscilloscope which provides an accurate DC voltage control after flyback of the sawtooth voltage. The sawtooth generator includes a balance circuit in the control loop and an error amplifier with symmetrical outputs. A current-mirrored copy of the integration current is supplied as the tail current for the balance circuit. The control loop is thus forced to control around a zero error signal.

Abstract: A drop-out detection circuit which supplies an output signal indicative of a drop-out within information reproduced from a storage medium, when a rectangular wave signal produced from a modulated signal carrying the reproduced information does not supply a trigger pulse within a prescribed pulse duration. The drop-out detection circuit comprises a first pulse generation part for supplying a first pulse signal having a low level for a prescribed pulse duration when the rectangular wave signal changes from a low level to a high level, a second pulse generation part for supplying a second pulse signal having a low level for the prescribed pulse duration when the rectangular wave signal changes from the high level to the low level, and a logic gate for outputting the output signal having a high-level pulse supplied only when the first pulse signal and the second pulse signal both having the high level is supplied for a time period exceeding the prescribed pulse duration.

Abstract: A multiplier comprises first and second squaring circuits each including first and second MOS transistors having their sources connected in common and third and fourth MOS transistors having their sources connected in common. The first and third transistors have a first gate W/L ratio and have their drains connected to each other, and the second and fourth transistors have their drains connected to each other and have a second gate W/L ratio different from the first ratio. Gates of the first and fourth transistors are connected to each other, and gates of the second and third transistors are connected to each other. A first input signal is supplied to the gates of the first and fourth transistors of each of the first and second squaring circuits, and a second input signal is supplied, without being inverted, to the gates of the second and third transistors of the first squaring circuit, and without being inverted, to the gates of the second and third transistors of the second squaring circuit.

Abstract: A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.

Abstract: A linear feedback shift register comprises a shift register formed of first to (n)th flipflops cascaded in such a manner that an output of a (i)th flipflop is connected to an input of a (i+1)th flipflop, where 2.ltoreq.n and 1.ltoreq.i.ltoreq.(n-1). First to (n)th output terminals are connected to outputs of the first to (n)th flipflops, respectively, and a clock terminal connected to a clock input of each of the flipflops. First to (n-1)th multiplexors of a "1-out-of-2" type are connected at their first input to a common preset value input terminal. Second inputs of the first to (n-1)th multiplexors are connected to the outputs of the first to (n-1)th flipflops, respectively. Each of the first to (n-1)th multiplexors has a control input connected to an individual control terminal.

Abstract: A drive circuit for a voltage-controlled type semiconductor device is provided which comprises ON gate drive circuit for supplying an ON control signal to a control electrode of the semiconductor device which performs a current switching, OFF gate drive circuit for supplying an OFF control signal to the control electrode of the semiconductor device, high voltage power source, connected to at least one of the ON gate drive circuit and OFF gate drive circuit, for supplying a control current of a predetermined current increase rate to the control electrode of the semiconductor device through at least one of the ON gate drive circuit and OFF gate drive circuit, low voltage power source, provided in juxtaposition with the high voltage power source, for supplying, to the control electrode, enough control current to hold the semiconductor device in a normal state, and switch for supplying an output of the high voltage power source to the control electrode in an earlier portion of a turn ON or a turn OFF period, and

Abstract: A monostable multivibrator comprises an input circuit receiving an trigger signal for generating an instantaneous pulse, a timing generation circuit receiving the instantaneous pulse for generating a timing defining signal after a predetermined time, and an output circuit for generating a output pulse starting in response to the instantaneous pulse and terminating at the timing defining signal.

Abstract: A circuit for generating two clock pulse trains of opposite polarity to one another each at a frequency of a single input clock pulse train including a flip-flop for providing the two output clock pulse trains, apparatus for placing the flip-flop in a first condition in response to the input clock pulse train, apparatus for producing signals for placing the flip flop in a second condition in response to the input clock pulse train after a first delay, apparatus for producing signals after a second delay in response to the first delayed signals, apparatus for equating the delays so that the first half of each clock pulse is the same length as the second half, and apparatus for comparing the input pulse train to the pulse trains produced to increase the frequency of the output trains produced responsive to the detection of a subharmonic of the input frequency.

Abstract: An electronic comparator circuit having a high speed during switch phase and combining the advantages of bipolar technology with those of CMOS technology. The circuit consists of a differential stage input circuit having a differential pair of bipolar transistors forming its outputs. The output stage contains a pair of MOS transistors having gate electrodes in common. The pair of MOS transistors is connected on one side to the outputs of the input portion and on the other side to a positive supply pole via a current mirror circuit. The output contains another pair of MOS transistors with gate electrodes in common connected between the outputs of the input portion and ground. The drain electrode of the first pair of MOS transistors forms the output for the comparator.

Abstract: A FSK data signal voltage inputted from an input terminal 4 is converted into current by a resistance R.sub.1 and then the current is differentially amplified with respect to a reference voltage of a capacitor C.sub.1 in a second differential amplifier circuit 2. As a result, a waveform-shaped signal is generated from each collector of transistors Q.sub.2 and Q.sub.3 constituting the second differential amplifier circuit 2. Meanwhile, the FSK data signal inputted from the input terminal 4, after an alternating current signal component thereof is removed, is applied to a third differential amplifier circuit 3 wherein a difference between the signal and the reference voltage of the capacitor C.sub.1 is amplified. Charging/discharging the capacitor C.sub.1 is controlled in response to an output of the third differential amplifier circuit 3.

Abstract: A technique for sensing the temperature of power MOS devices contemplates a main transistor and monolithically formed sense transistor. A resistor, which may integrated into the device or may be off chip, is connected between the respective source nodes of the main transistor and the sense transistor (as in a normal current mirror). However, the respective gate nodes of the main transistor and the sense transistor are not directly connected to each other (in contrast to the normal current mirror configuration where the respective gate nodes of the main transistor and the sense transistor are directly connected). Rather, the sense transistor gate node is coupled to the output terminal of an operational amplifier. The amplifier, has a first input terminal coupled to a reference voltage and a second, complementary, input terminal coupled to the sense transistor source node.

Abstract: A non-linear transimpedance amplifier utilizing a reset integrator and having a broad dyamic range for amplifying an input signal over an extended range of levels is disclosed. The non-linear transimpedance amplifier comprises an accumulator for accumulating a charge representative of the input signal, a comparator for comparing the output of the first circuit to a reference voltage, a sample and hold for providing a voltage representative of the level of a time varying waveform at the instant during which the accumulator saturates, and a summer for summing a signal representative of the accumulated charge and the signal representative of the level of the time varying waveform. The output signal is representative of the input signal when the accumulator is unsaturated as well as when the accumulator is saturated. The present invention may also be operated as a linear amplifier. It finds particular application in the input circuits of infrared detector elements.

Abstract: There is disclosed a self-regulating clock generator for providing an output clock signal to clock a CMOS microprocessor. The output clock signal has first and second phases of sufficient length to accommodate microprocessor speed paths and is provided in response to an input clock signal having a frequency and a duty cycle within a wide range of frequencies and duty cycles. The clock generator includes a latch arranged to be set and reset by the input clock signal and having an output for providing the output clock signal. A delay circuit is coupled to the latch output and enables the setting and resetting of the latch to establish the phase lengths. Also disclosed is a second clock generator which includes a pair of latches and a pair of delay circuits for providing an output clock signal having first and second phases of different lengths.

Abstract: A zero crossing detector arrangement which is operable on successive samples of an analogue signal comprises a first stage (3) which includes adders and dividers (A,D) for affording a first output (b4) corresponding to the average of two successive samples (x1,x2), a gate (G2) for affording a first estimate (B3) in dependence upon the relative signs of one of the successive samples (x1) and the first output and a second stage 4 which includes adders and dividers (A,D) for affording a second output (b6) corresponding to the average of the first output (b4) and a selected one of the successive samples (x1,x2) and a gate (G2) for affording a second estimate (B2) in dependence upon the relative signs of the second output (b6) and a selected one of either the one of the successive samples (x1,x2) or said first output (b4), the first estimate (B3) and the second estimate (B2) constituting an output word which is indicative of the position of a zero crossing.