Abstract: A data synchronizer that operates at two to four times greater clock and data rates than previous data synchronizers. By using a positive feedback, self latching gate as the first memory element, rather than a cross-coupled device such as a flip-flop, such rates are attained without inducing metastable oscillation. The positive feedback, self latching gate is far less prone to metastable oscillation since it does not have two cross-coupled devices fighting each other to resolve the proper response to an input. Instead, the self latching gate latches up if a data HIGH is present during a clock HIGH, and remains LOW otherwise. External circuitry resets the self latching gate to the LOW state before the start of each clock HIGH cycle to remove any previous latched state. The self latching gate output is then synchronously sampled by a type D flip-flop to provide a completely synchronized data output.

Abstract: A clock circuit for generating two clock signals, one (CLK) having stretched clock phases on a cycle by cycle basis, and the second (2X CLK) being a clock signal having a frequency twice the frequency of the first clock signal which is phase and edge coherent with the first clock signal, including the stretched clock phases. The circuit inputs a signal generated by an oscillator which is twice the frequency of the CLK signal which is then used to generate the CLK signal for use by a microprocessor, either phase of which can be stretched on demand, while the second 2X CLK signal remains phase coherent with the microprocessor CLK signal.