Patents Examined by Son L. Mai
  • 3D memory device including shared select gate connections between memory blocks
    Patent number: 11164629
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Nonvolatile memory device and operating method of the same
    Patent number: 11164631
    Abstract: A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other, and a control logic configured to set a voltage level of a second voltage applied for a second memory operation to one of the second memory cells in the second memory stack based on a first voltage applied to one of the first memory cells in the first memory stack in a first memory operation. The second memory stack is vertically stacked on the first memory stack. Cell characteristics of the one of the first memory cells is determined using the first voltage.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: November 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-chul Park, Youn-yeol Lee, Seul-bee Lee, Kyung-sub Lim
  • Storage device adjusting a timing of a data signal and a data strobe signal
    Patent number: 11158359
    Abstract: A storage device includes a nonvolatile memory device, and a controller that exchanges a data signal with the nonvolatile memory device through a data input and output line and exchanges a data strobe signal with the nonvolatile memory device through a data strobe line. In a training operation, at least one of the nonvolatile memory device and the controller performs a coarse training of adjusting a delay of the data signal with a first stride and a fine training of adjusting the delay of the data signal with a second stride smaller than the first stride.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: October 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyungjin Kim, Soong-Man Shin
  • Operating method of controller
    Patent number: 11145375
    Abstract: A memory system includes a nonvolatile memory device including a plurality of memory cells; and a controller including a control unit and a random-access memory, and configured to determine, by applying a program verify voltage to at least one memory cell to be programmed with program data, whether the program data is programmed, wherein the control unit determines percentages of a count of read requests received from a host device and a count of program requests received from the host device, and adjusts a level of the program verify voltage based on the percentages.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang Hune Jung
  • Method for controlling multi-cycle write leveling process in memory system
    Patent number: 11145343
    Abstract: A method for controlling a multi-cycle write leveling process in a memory system is provided. After a write leveling process is completed and before a write training process is performed, the multi-cycle write leveling process is performed. Consequently, when a DDR memory of the memory system receives a clock signal and a first data strobe signal, the DDR memory can confirm that the signal edges of the clock signal and the first data strobe signal are aligned with each other and the signal edges are accurate.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: October 12, 2021
    Assignee: FARADAY TECHNOLOGY CORPORATION
    Inventors: Sivaramakrishnan Subramanian, Hong-Yi Wu, Sridhar Cheruku, Ko-Ching Chao
  • Memory device
    Patent number: 11145346
    Abstract: According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: October 12, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Yorinobu Fujino
  • Read model of memory cells using information generated during read operations
    Patent number: 11133083
    Abstract: A memory sub-system configured to generate or update a model for reading memory cells in a memory device. For example, in response to a processing device of a memory sub-system transmitting to a memory device read commands that are configured to instruct the memory device to retrieve data from a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells. The changes can be a result of damage, charge loss, read disturb, cross-temperature effect, etc.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Memory device for changing pass voltage
    Patent number: 11127472
    Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Jun Lee, Seung Bum Kim, Il Han Park
  • Devices and methods to program a memory cell
    Patent number: 11120873
    Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 14, 2021
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Umberto Di Vincenzo, Carlo Lisi
  • Power switching for embedded memory
    Patent number: 11120844
    Abstract: Methods, systems, and devices for power switching for embedded memory are described. A system may be configured with circuitry (e.g., power supply switching circuitry) coupled with or between a power supply and a power input node of a memory device, which may support selectively coupling or isolating the memory device and the power supply based on various conditions. For example, the circuitry may be configured for a selective coupling or a selective isolation based on a voltage level of the power supply satisfying various voltage thresholds. The circuitry may also be configured to support various input or output signaling, such as transmitting an indication of an isolation from the power supply, transmitting an indication to perform a memory initialization, or receiving an indication or command to perform a power cycle.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Rainer Frank Bonitz
  • Non-volatile memory device
    Patent number: 11114180
    Abstract: A non-volatile memory device includes a first memory cell array, a first error correction code (ECC) decoder and a controller. The first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary. The first ECC decoder is coupled to the first memory cell array, performs an ECC operation on read-out data from first memory cell array. The controller is coupled to the first memory cell array and the first ECC decoder, adjusts the first address boundary according to a first ECC failure bit number.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: September 7, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Chi-Shun Lin, Ngatik Cheung, Douk-Hyoun Ryu, Ming-Huei Shieh, Chuen-Der Lien
  • Memory device for compensating for current of off cells and operating method thereof
    Patent number: 11114160
    Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Venkataramana Gangasani, Moo-Sung Kim, Tae-Hui Na, Jun-Ho Shin
  • Memory controller with clock-to-strobe skew compensation
    Patent number: 11100976
    Abstract: An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: August 24, 2021
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Sensing circuits for charge trap transistors
    Patent number: 11101010
    Abstract: The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 24, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Eric D. Hunt-Schroeder, Sebastian T. Ventrone, James A. Svarczkopf, Igor Arsovski
  • Semiconductor memory device and operating method thereof
    Patent number: 11094369
    Abstract: A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits, each of the plurality of address storing circuits suitable for storing a sampling address as a latch address, a valid bit indicating whether the latch address is valid, and a valid-lock bit indicating whether the latch address is accessed more than a certain number of times, each of the plurality of address storing circuits further suitable for outputting the latch address as a target address according to the valid bit and valid-lock bit; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to a refresh command.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Nogeun Joo, Jungho Lim, Byeongchan Choi, Jeongtae Hwang
  • Semiconductor memory devices and methods of operating semiconductor memory devices
    Patent number: 11094390
    Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungryun Kim, Yoonna Oh, Hohyun Shin, Jaeho Lee
  • Suppression of program disturb with bit line and select gate voltage regulation
    Patent number: 11081194
    Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: August 3, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
  • Binary weighted voltage encoding scheme for supporting multi-bit input precision
    Patent number: 11081148
    Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
  • Semiconductor memory device
    Patent number: 11081188
    Abstract: According to one embodiment, a semiconductor memory device includes a controller configured to execute a read operation. In the read operation, the controller is configured to: apply first and second read voltages to a word line, read data at each of first and second times, apply the first voltage to the source line at each of the first and second times, apply a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and apply a third voltage to the source line during the application of the second read voltage to the word line and before the second time.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 3, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Kosuke Yanagidaira, Hiroshi Tsubouchi
  • Semiconductor device, electronic component, and electronic device
    Patent number: 11074953
    Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Shunpei Yamazaki