Abstract: A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.

Abstract: Systems, devices, circuits, methods, and non-transitory computer readable media that enable storing and searching arbitrary segments of ranges of analog values are disclosed. Various analog content addressable memory (aCAM) circuit implementations having the capability to store and search outside of a range of values, within any of multiple disjoint ranges, or outside of multiple ranges are disclosed. The disclosed aCAM circuit implementations make searching for complex input features more flexible and efficient, thereby yielding a technological improvement over conventional solutions. In some implementations, an aCAM may include multiple pull-down transistors connected in series to a match line that is pre-charged, in which case, the aCAM detects a match if the match line is not discharged by the pull-down transistors, which occurs if at least one pull-down transistor is in an OFF state. In other implementations, an aCAM includes pass gates connected to a match line to detect a match.

Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.

Abstract: A semiconductor memory device includes a memory string and a control logic. The memory string is connected between a common source line and a bit line and includes at least one first select transistor, a plurality of memory cells, and a plurality of second select transistors. The control logic is configured to apply a first voltage to a first group among second select lines respectively connected to the second select transistors, float a second group among the second select lines and then apply an erase voltage to the common source line, during an erase operation.

Abstract: A pseudo-analog memory computing circuit includes at least one input circuit, at least one output circuit and at least one pseudo-analog memory computing unit. Each pseudo-analog memory computing unit is coupled between one of the at least one input circuit and one of the at least one output circuit and has at least one weight mode. Each pseudo-analog memory computing unit generates at least first computing result for a coupled output circuit according to a weight of a selected weight mode and at least one input signals of a coupled input circuit.

Abstract: A memory device includes a memory cell array including memory cells connected to word lines and bit lines. Each of the memory cells includes a switch element and a memory element, and has a first state or a second state in which a threshold voltage is within a first voltage range or a second voltage range, lower than the first voltage range. A memory controller is configured to execute a first read operation for the memory cells using a first read voltage, higher than a median value of the first voltage range, program first defect memory cells turned off during the first read operation to the first state, execute a second read operation for the memory cells using a second read voltage, lower than a median value of the second voltage range, and execute a repair operation for second defect memory cells turned on during the second read operation.

Abstract: An integrated circuit includes a driving circuit and an enable control circuit. The driving circuit is configured to perform a setup operation based on a first driving current and perform a preset operation, using different driving currents, based on a first enable signal and a second enable signal. The enable control circuit is configured to generate the first and second enable signals.

Abstract: A non-volatile memory includes a plurality of blocks and a controller. Each of the plurality of blocks includes a plurality of pages, and each of the plurality of pages includes a plurality of storage units. The controller is configured to perform: receiving an erase command for a target block of the plurality of blocks; executing a read operation on each page of the target block; and executing a first erase operation to apply word line voltages to the plurality of pages, where the word line voltages are determined by a read result of the read operation of each page. An operation method of a non-volatile memory and an electronic device are also provided.

Abstract: Disclosed is a protection circuit of a memory in a display panel. The circuit includes: a timing controller, for outputting a first control signal; a memory, for storing software data of the timing controller; a power supply circuit, for outputting a power signal; and a monitor circuit, having three input ends and a signal output end, two input ends being respectively connected to the power supply circuit and a control signal output end, and the other one input end being input with a write control signal; the monitor circuit controls the memory to be in a write protection state when in a normal state, and controls the memory to be in a write enable state when a level state collection of the power signal, the first control signal, and the write control signal satisfies a preset level state collection.

Abstract: The present disclosure includes apparatuses and methods related to memory topologies. An apparatus may include a first plurality of clam-shell paired memory devices arranged in a star connection topology, each clam-shelled pair of the first plurality of memory devices being coupled by a respective matched branch to a first common command address signal trace. The apparatus may include a second plurality of memory devices coupled to a second common command address signal trace.

Abstract: A memory system includes a memory controller and a memory device. The memory controller generates refresh commands periodically by an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during a refresh cycle time. The memory device includes a memory cell array including memory cells connected to a plurality of wordlines, a temperature sensor configured to provide temperature information by measuring an operation temperature of the memory cell array and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller varies a hammer ratio of a unit hammer execution number of the hammer refresh operation executed during the refresh cycle time with respect to a unit normal execution number of the normal refresh operation executed during the refresh cycle time.

Abstract: A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.

Abstract: A semiconductor device that can automatically transition from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes a DPD controller supporting the DPD mode and multiple internal circuits. The DPD controller measures a time since a time point of entering the standby mode and generates multiple power down enable signals for further reducing power consumption in the standby mode in response to elapse of a measurement time, so that operations of the multiple internal circuits are stopped in stages.

Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.

Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a DBI encoder configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, a DBI port being configured to receive the DBI data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port; a data buffer module connected to the memory bank through the global bus; and a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to Low.

Abstract: Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.

Abstract: The present disclosure provides an operation method related to a post package repair (PPR) function in a dynamic random access memory (DRAM) device. The method for operating a post package repair (PPR) function of a memory device is disclosed. The method includes providing a memory bank, which includes a memory array and a sense amplifier adjacent to the memory array, wherein the memory array comprises at least one defective row and at least one associated row, and the at least one associated row is electrically connected to the sense amplifier by a plurality of bit lines. The method also includes arranging a redundant row adjacent to the memory array, wherein the redundant row is electrically connected to the sense amplifier by the plurality of bit lines.