Abstract: Semiconductor device includes a well region formed in an active region of a semiconductor substrate, a gate electrode formed on the well region via a gate dielectric film, and a source region and a drain region formed in the well region. At the vicinity of both end portions of the active region in the first direction, a first region and a second region having the same conductivity type as the well region and having impurity concentration higher than that of the well region are formed in the well region. The first region and the second region are spaced from each other in a second direction perpendicular to the first direction, and at least a portion of each of them is located under the gate electrode. The first region and the second region are not formed at the center portion of the active region in the first direction.

Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

Abstract: A system, method and device for use as a reflector for a light emitting diode (LED) are disclosed. The system, method and device include a first layer designed to reflect transverse-electric (TE) radiation emitted by the LED, a second layer designed to block transverse-magnetic (TM) radiation emitted from the LED, and a plurality of ITO layers designed to operate as a transparent conducting oxide layer. The first layer may be a one-dimension (1D) distributed Bragg reflective (DBR) layer. The second layer may be a two-dimension (2D) photonic crystal (PhC), a three-dimension (3D) PhC, and/or a hyperbolic metamaterial (HMM). The 2D PhC may include horizontal cylinder bars, vertical cylinder bars, or both. The system, method and device may include a bottom metal reflector that may be Ag free and may act as a bonding layer.

Abstract: A semiconductor device includes a substrate, first and second semiconductor strips, a dummy fin structure, first and second channel layers, a gate structure, and crystalline and amorphous hard mask layers. The first and second semiconductor strips extend upwardly from the substrate and each has a length extending along a first direction. The dummy fin structure is laterally between the first and second semiconductor strips. The first and second channel layers extend in the first direction above the first and second semiconductor strips and are arranged in a second direction substantially perpendicular to the substrate. The crystalline hard mask layer extends upwardly from the dummy fin structure and has an U-shaped cross section. The amorphous hard mask layer is in the crystalline hard mask layer. The amorphous hard mask layer has an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.

Abstract: A method includes forming a semiconductor fin on a substrate; conformally forming a dielectric layer over the semiconductor fin; depositing an oxide layer over the dielectric layer; etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin; conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer; planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin; forming a gate structure extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure.

Abstract: An epitaxial wafer that includes a silicon wafer and an epitaxial layer on the silicon wafer. The silicon wafer contains hydrogen that has a concentration profile including a first peak and a second peak. A hydrogen peak concentration of the first peak and a hydrogen peak concentration of the second peak are each not less than 1×1017 atoms/cm3.

Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

Abstract: The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Abstract: A display apparatus includes a substrate, a display unit disposed on the substrate, an insulating layer disposed on the substrate, a power supply wire disposed on the insulating layer outside the display unit, and a cladding layer. The display unit includes a pixel circuit and a display element electrically connected to the pixel circuit. The insulating layer extends from the display unit to an edge of the substrate. The power supply wire is electrically connected to the display element and includes an alignment pattern that exposes at least a portion of the insulating layer. The cladding layer covers an inner surface of the alignment pattern and contacts the at least a portion of the insulating layer.

Abstract: An OLED display panel and a display device are provided. A photoresist structure of a color filter layer is a stack of two defining layers, a sloped surface is defined between corresponding defining areas of two defining layers, and a color resist unit of the color filter layer is formed in corresponding color resist defining areas and corresponds to a light-emitting unit, which reduces a usage of color filter materials and prevents solvent volatilizing to the environment by using solvent-free color filter materials.

Abstract: There is provided a method of manufacturing a semiconductor device, including forming a metal nitride film substantially not containing a silicon atom on a substrate by sequentially repeating: (a) supplying a metal-containing gas and a reducing gas, which contains silicon and hydrogen and does not contain a halogen, to the substrate in a process chamber by setting an internal pressure of the process chamber to a value which falls within a range of 130 Pa to less than 3,990 Pa during at least the supply of the reducing gas, wherein (a) includes a timing of simultaneously supplying the metal-containing gas and the reducing gas; (b) removing the metal-containing gas and the reducing gas that remain in the process chamber; (c) supplying a nitrogen-containing gas to the substrate; and (d) removing the nitrogen-containing gas remaining in the process chamber.

Abstract: A flexible display panel is provided, which includes a base substrate, a thin film transistor (TFT) array layer, and an encapsulation layer. The TFT array layer includes an inorganic layer. An organic layer is disposed on the TFT array layer in a non-display region. The organic layer is defined with a hollow structure at least penetrating the organic layer and the encapsulation layer covers the hollow structure. The organic layer includes a planarization layer, a pixel definition layer, and a support layer. The hollow structure includes grooves with different groove levels, which improves a bending resistance of the flexible display panel and prevents cracks from extending to a display region.

Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.