Patents Examined by Sonya McCall-Shepard
  • Patent number: 11069806
    Abstract: An integrated circuit includes a logic circuit and an amplifying circuit, in particular a low-noise amplifying circuit. The amplifying circuit includes at least one first transistor. The gate of the first transistor is coupled to a signal input terminal, the source region and the drain region of the first transistor are formed respectively in the well region of the first transistor on both sides of the gate, wherein the source region is coupled to a reference voltage terminal, and the sheet resistance of the source region is lower than that of the drain region. The logic circuit includes at least one second transistor. The sheet resistances of the source region and the drain region of the second transistor are equal.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 20, 2021
    Assignee: RichWave Technology Corp.
    Inventors: Chuan-Chen Chao, Shyh-Chyi Wong, Shu-Yuan Hsu
  • Patent number: 11062075
    Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Patent number: 11062908
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Patent number: 11049771
    Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate, placing a first stencil having a first openwork pattern on the substrate, applying a first material onto the substrate through the first stencil, and removing the first stencil from the substrate. The first material includes a transparent material. The method also includes placing a second stencil having a second openwork pattern on the substrate, applying a second material onto the substrate through the second stencil, and removing the second stencil from the substrate. The second material includes a light-shielding material, and the second openwork pattern is different from the first openwork pattern.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: June 29, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Han-Liang Tseng, Hsin-Hui Lee, Hsueh-Jung Lin
  • Patent number: 11049940
    Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Juntao Li, Heng Wu
  • Patent number: 11037840
    Abstract: A plurality of semiconductor devices (5) are formed on a semiconductor wafer (1). A film thickness measurement wiring pattern (3,4) is formed on a dicing line (6,7) defining the plurality of semiconductor devices (5). An SOG film (10) is formed on the semiconductor devices (5) and the film thickness measurement wiring pattern (3,4). A film thickness of the SOG film (10) at a central part of the film thickness measurement wiring pattern (3,4) is measured. The film thickness measurement wiring pattern (3,4) is a rectangular pattern having long sides parallel to the dicing line (3,4).
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 15, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yuji Kawasaki
  • Patent number: 11037909
    Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung
  • Patent number: 11031409
    Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is disposed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is disposed on the memory region and a cell boundary structure is formed on the isolation structure including a boundary sidewall spacer. A protecting dielectric layer is disposed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high ? etch residue during formation of the logic device structure with HKMG technology.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Wei Cheng Wu, Chih-Pin Huang
  • Patent number: 11024767
    Abstract: A system, method and device for use as a reflector for a light emitting diode (LED) are disclosed. The system, method and device include a first layer designed to reflect transverse-electric (TE) radiation emitted by the LED, a second layer designed to block transverse-magnetic (TM) radiation emitted from the LED, and a plurality of ITO layers designed to operate as a transparent conducting oxide layer. The first layer may be a one-dimension (1D) distributed Bragg reflective (DBR) layer. The second layer may be a two-dimension (2D) photonic crystal (PhC), a three-dimension (3D) PhC, and/or a hyperbolic metamaterial (HMM). The 2D PhC may include horizontal cylinder bars, vertical cylinder bars, or both. The system, method and device may include a bottom metal reflector that may be Ag free and may act as a bonding layer.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 1, 2021
    Assignee: Lumileds LLC
    Inventors: Toni Lopez, Venkata Ananth Tamma
  • Patent number: 11024798
    Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong
  • Patent number: 11024803
    Abstract: A method of forming a resistive random access memory (RRAM) element, the method includes forming a Silicon layer on an oxide layer, depositing a thin film dopant layer on the Silicon layer, and controlling a concentration of the dopant in the thin film dopant layer.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Matthew Warren Copel, James Bowler Hannon, Satoshi Oida
  • Patent number: 11011389
    Abstract: A semiconductor device assembly and method of providing a semiconductor device assembly. The method includes providing a flexible interposer, providing a first redistribution layer on the flexible interposer, and providing a second redistribution layer on a portion of the first redistribution layer. The second redistribution layer is provided by additive manufacturing. The first redistribution layer may be deposited in a clean room environment. The first redistribution layer may be deposited via chemical deposition or physical deposition. A semiconductor device is attached to the first redistribution layer. The flexible interposer may be attached to a board with the semiconductor device being electrically connected to the board via the first redistribution layer, the flexible interposer, and the second redistribution layer. The flexible interposer may be attached to a flexible hybrid electronic (FHE) board.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 18, 2021
    Assignee: THE BOEING COMPANY
    Inventors: John E. Rogers, John Dalton Williams
  • Patent number: 11004935
    Abstract: The present invention discloses a rugged power semiconductor field effect transistor structure, and through a special design, it solves the problem that the activation under a transient condition may result in failures on the device, so that there is no parasitic BJT, and thus the device is more rugged.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 11, 2021
    Inventor: Wai Yee Liu
  • Patent number: 11002996
    Abstract: A metallic quantum well may be formed by interposing a layer of metallic well material two layers of barrier material. Two or more metallic quantum wells may be combined to form a coupled metallic quantum well. The absorption spectrum and the emission spectrum of the coupled metallic quantum well may be tuned by at least adjusting the dimensions of the individual metallic quantum wells and/or the materials forming the metallic quantum wells. The metallic quantum well and/or the coupled metallic quantum well may exhibit sufficient nonlinearity even at a miniaturized scale. As such, the metallic quantum well and/or coupled metallic quantum well may be used for a variety of on-chip applications including, for example, as part of an on-chip pulse limiter, an on-chip super-continuum generator, and/or the like.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: May 11, 2021
    Assignee: The Regents of the University of California
    Inventors: Zhaowei Liu, Yuzhe Xiao, Haoliang Qian
  • Patent number: 10982327
    Abstract: The present disclosure relates to a method of chemical vapor deposition (CVD). In some embodiments, a process gas is applied into a vacuum chamber. The process gas is guided downstream the vacuum chamber through a shower head arranged under the gas import, where the process gas is redirected to be laterally unevenly distributed under the shower head. A density of the process gas increases from a center region to a peripheral region of the vacuum chamber. The process gas is then deposited onto a first substrate to form a precursor material with an uneven thickness profile as a result of uneven distribution of the process gas. The shower head has multiple control zones each having a plurality of holes disposed through the shower head.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Wei Fang, Yi Hsun Chiu, Cho-Han Li, Yao Fong Dai
  • Patent number: 10985104
    Abstract: A semiconductor device according to an embodiment includes a first electrode pad containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; an electrode layer containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; and a semiconductor layer provided between the first electrode pad and the electrode layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: April 20, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Seiji Inumiya, Kyoichi Suguro
  • Patent number: 10985280
    Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10975473
    Abstract: The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a shower head arranged under the gas import having a plurality of holes formed there through. The shower head redistributes the process gas to form a precursor material with an uneven thickness that matches a remove profile of a subsequent CMP process. As a result, planarity of the formed layer after the CMP process is improved.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Wei Fang, Yi Hsun Chiu, Cho-Han Li, Yao Fong Dai
  • Patent number: 10978490
    Abstract: An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO3(ZnO)m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: April 13, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunichi Ito, Toshinari Sasaki, Miyuki Hosoba, Junichiro Sakata
  • Patent number: 10978593
    Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung