Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first pair of opposing sidewalls that define a trench. The trench extends into a front-side surface of the substrate. A first source/drain region is disposed along the front-side surface of the substrate. A second source/drain region is disposed along the front-side surface of the substrate. A gate structure is disposed within the trench and is arranged laterally between the first source/drain region and the second source/drain region. The gate structure fills the trench and extends along the first pair of opposing sidewalls to an upper surface of the substrate. A bottom surface of the gate structure is disposed below a bottom surface of the first source/drain region.

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.

Abstract: A transistor includes a vertical stack containing, in order from bottom to top or from top to bottom, a gate electrode, a gate dielectric, and an active layer and located over a substrate. The active layer includes an amorphous semiconductor material. A crystalline source region including a first portion of a crystalline semiconductor material overlies, and is electrically connected to, a first end portion of the active layer. A crystalline drain region including a second portion of the crystalline semiconductor material overlies, and is electrically connected to, a second end portion of the active layer.

Abstract: A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.

Abstract: A wavelength conversion element includes a substrate, reflection layer on the substrate, wavelength conversion layer in the reflection layer and converting a light in a first wavelength range into a light in a second wavelength range, structure in the wavelength conversion layer and scattering a part of the light in the first wavelength range, and optical layer in the structure, reflecting a part of the light in the first wavelength range, transmitting another part of the light in the first wavelength range, and transmitting the light in the second wavelength range. The structure includes a first structure portion, second structure portion, and planar portion between the first and second structure portions, the optical layers in the first and second structure portions have first reflectance for the light in the first wavelength range, and the optical layer in the planar portion has second reflectance.

Abstract: A pixel may include first and second areas sectioned from each other in a first direction; 1-1-th to 4-1-th electrodes successively arranged in the first area in a second direction intersecting the first direction; 1-2-th to 4-2-th electrodes successively arranged in the second area in the second direction; light emitting elements disposed between two adjacent electrodes of the 1-1-th to 4-1-th electrodes of the first area; light emitting elements disposed between two adjacent electrodes of the 1-2-th to 4-2-th electrodes of the second area; a first conductive pattern disposed in the first area, and electrically connecting the 2-1-th and 3-1-th electrodes; a second conductive pattern disposed over the first and second areas, and electrically connecting the 4-1-th electrode of the first area with the 1-2-th electrode of the second area; and a third conductive pattern disposed in the second area and electrically connecting the 2-2-th and 3-2-th electrodes.

Abstract: A display panel, a manufacturing method thereof, and a bonding structure are provided. The display panel includes a first body electrode and a second body electrode disposed on a same layer on a substrate and disposed oppositely. A first conductive electrode is disposed on the first body electrode. A light-emitting device includes a first lead and a second lead disposed opposite to each other. The first lead is disposed to contact the first body electrode and the first conductive electrode. The second lead contacts the second body electrode.

Abstract: A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second dielectric features and a first semiconductor layer disposed between the first and second dielectric features. The structure further includes an isolation layer disposed between the first and second dielectric features, and the isolation layer is in contact with the first and second dielectric features. The first semiconductor layer is disposed over the isolation layer. The structure further includes a gate dielectric layer disposed over the isolation layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer has an end extending to a level between a first plane defined by a first surface of the first semiconductor layer and a second plane defined by a second surface opposite the first surface.

Abstract: The present application provides a display panel. The display panel includes a plurality of data lines, a plurality of constant voltage traces, and a plurality of drive traces located in a display area. The display panel further includes a first metal layer, a second metal layer, and a shield layer between the first metal layer and the second metal layer, wherein the first metal layer includes a gate trace, the shield layer includes a plurality of shield traces, and the second metal layer includes the drive trace. An overlap region of the drive trace and the gate trace on the shield layer overlaps with the shield trace.

Abstract: A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.

Abstract: A flexible organic light-emitting diode (OLED) substrate includes a flexible substrate, an inorganic barrier layer, an OLED device, and an adhesive-filling layer. The inorganic barrier layer is disposed on the flexible substrate. The OLED device is disposed on the inorganic barrier layer. The adhesive-filling layer covers the OLED device and the inorganic barrier layer. The flexible substrate further comprises a base substrate, a bending portion, and a covering portion. A thin film transistor layer is disposed on the base substrate, and the bending portion is connected to the base substrate and the covering portion. The covering portion covers the adhesive-filling layer and is stacked above the base substrate.

Abstract: Reflected light from a back-illuminated photoelectric conversion element is to be reduced. The photoelectric conversion element includes an on-chip lens, a substrate, a front-surface-side reflective film, and a back-surface-side reflective film. The on-chip lens condenses incident light. A photoelectric conversion unit that performs photoelectric conversion on the condensed incident light is disposed in the substrate, and the back surface side of the substrate is irradiated with the condensed incident light. The front-surface-side reflective film is disposed on the front surface side that is a different side from the back surface side of the substrate, and reflects transmitted light that is the incident light having passed through the photoelectric conversion unit. The back-surface-side reflective film is disposed on the back surface side of the substrate, has an opening of substantially the same size as the condensing size of the condensed incident light, and further reflects the reflected transmitted light.

Abstract: A transparent display device may prevent deterioration of light transmittance, which is caused by a repair line, from occurring. The transparent display device comprises a substrate provided with transmissive areas, a non-transmissive area disposed between the transmissive areas, and a plurality of subpixels disposed in the non-transmissive area, a first electrode provided in each of the plurality of subpixels, a driving transistor connected with the first electrode of each of the plurality of subpixels, including an active layer, a gate electrode, a source electrode and a drain electrode, a capacitor connected to the driving transistor of each of the plurality of subpixels, including a first capacitor electrode and a second capacitor electrode, and an anode line extended from the first electrode of each of the plurality of subpixels to at least partially overlap a driving transistor or a capacitor of an adjacent subpixel of the same color.

Abstract: A semiconductor device includes a silicon substrate and a fin formed above the substrate. The fin provides active regions for two devices, such as gate-all-around transistors. The semiconductor device also includes a fin-insulating structure positioned to electrically isolate the active regions for the two devices. The fin-insulating structure is formed in a trench, with a first portion adjacent the fin and a second portion below the fin and extending into the substrate. The fin-insulating structure includes an oxide liner in the second portion of the trench, but not the first portion. The fin-insulating structure is further filled with an insulating material such as silicon nitride.

Abstract: An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

Abstract: A display device includes a first transistor configured to control a driving current flowing from a first electrode to a second electrode according to a voltage applied to a gate electrode of the first transistor, and a second transistor between the second electrode of the first transistor and the gate electrode of the first transistor, the second transistor including a first sub-transistor and a second sub-transistor. A same scan signal is to be transmitted to a gate electrode of the first sub-transistor and a gate electrode of the second sub-transistor. A gate insulating layer of the first sub-transistor includes a first thickness. A gate insulating layer of the second sub-transistor includes a second thickness smaller than the first thickness.