Abstract: A transparent display device may prevent deterioration of light transmittance, which is caused by a repair line, from occurring. The transparent display device comprises a substrate provided with transmissive areas, a non-transmissive area disposed between the transmissive areas, and a plurality of subpixels disposed in the non-transmissive area, a first electrode provided in each of the plurality of subpixels, a driving transistor connected with the first electrode of each of the plurality of subpixels, including an active layer, a gate electrode, a source electrode and a drain electrode, a capacitor connected to the driving transistor of each of the plurality of subpixels, including a first capacitor electrode and a second capacitor electrode, and an anode line extended from the first electrode of each of the plurality of subpixels to at least partially overlap a driving transistor or a capacitor of an adjacent subpixel of the same color.

Abstract: A semiconductor device includes a silicon substrate and a fin formed above the substrate. The fin provides active regions for two devices, such as gate-all-around transistors. The semiconductor device also includes a fin-insulating structure positioned to electrically isolate the active regions for the two devices. The fin-insulating structure is formed in a trench, with a first portion adjacent the fin and a second portion below the fin and extending into the substrate. The fin-insulating structure includes an oxide liner in the second portion of the trench, but not the first portion. The fin-insulating structure is further filled with an insulating material such as silicon nitride.

Abstract: An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

Abstract: A display device includes a first transistor configured to control a driving current flowing from a first electrode to a second electrode according to a voltage applied to a gate electrode of the first transistor, and a second transistor between the second electrode of the first transistor and the gate electrode of the first transistor, the second transistor including a first sub-transistor and a second sub-transistor. A same scan signal is to be transmitted to a gate electrode of the first sub-transistor and a gate electrode of the second sub-transistor. A gate insulating layer of the first sub-transistor includes a first thickness. A gate insulating layer of the second sub-transistor includes a second thickness smaller than the first thickness.

Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

Abstract: The invention relates to an optoelectronic semiconductor chip comprising a semiconductor layer sequence with a first semiconductor layer, a second semiconductor layer and an active layer between the first and the second semiconductor layers. The optoelectronic semiconductor chip further comprises a first contact structure with a plurality of first contact pins and a first contact layer for electrically contacting the first semiconductor layer and a second contact structure for electrically contacting the second semiconductor layer. The first semiconductor layer is disposed between the first contact layer and the active layer. The first contact pins are disposed between the first contact layer and the first semiconductor layer and are separated and spaced at a distance from one another in the lateral direction. An electrical connection with an electrical resistance between the first contact layer and the first semiconductor layer is formed by each first contact pin.

Abstract: A semiconductor device includes an active region on a substrate, a gate structure on the substrate and intersecting the active region, a source/drain region on the active region on both sides of the gate structure and including silicon (Si), and a contact structure on the source/drain region. The source/drain region includes a shallow doping region doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region. A concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to an upper surface of the substrate.

Abstract: There is provided a technique that includes: (a) supplying a molybdenum-containing gas containing molybdenum and oxygen to a substrate in a process chamber; (b) supplying an additive gas containing hydrogen to the substrate; and (c) supplying a reducing gas containing hydrogen and having a chemical composition different from that of the additive gas to the substrate, wherein at least two of (a), (b), and (c) are performed simultaneously or to partially overlap with each other in time one or more times or (a), (b), and (c) are performed sequentially one or more times to form a molybdenum film on the substrate.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Abstract: A method of producing an optoelectronic component includes providing a semiconductor wafer with a functional semiconductor layer that has electronic control elements, and a growth layer; generating a plurality of recesses in the semiconductor wafer exposing the growth layer in places; and epitaxially growing a plurality of semiconductor layer stacks on the exposed growth layer, wherein a surface of the exposed growth layer is used as a growth surface for the semiconductor layer stacks, and the growth surface is inclined to a main extension plane of the semiconductor wafer.

Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Abstract: A bidirectional switch module includes a plurality of bidirectional switches and a mount board. Each of the plurality of bidirectional switches includes a first source electrode, a first gate electrode, a second gate electrode, and a second source electrode. On the mount board, the plurality of bidirectional switches are mounted. In the bidirectional switch module, the plurality of bidirectional switches are connected in parallel.

Abstract: Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate.

Abstract: According to an aspect of the present disclosure, the display device includes a lower substrate and a plurality of pixel substrates disposed on the lower substrate. The display device also includes a plurality of transistors disposed on the plurality of pixel substrates and a planarization layer disposed on the plurality of pixel substrates to cover upper portions of the plurality of transistors. The display device further includes a plurality of individual connection pads and a common connection pad disposed on the planarization layer. The display device also includes a plurality of light emitting diodes disposed on the plurality of individual connection pads and the common connection pad. At least one of the plurality of individual connection pads and the common connection pad may have a multilayer structure.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; patterning the epitaxial layer into a semiconductor fin; depositing a conformal semiconductor capping layer over the semiconductor fin, wherein the conformal semiconductor capping layer has a first portion that is amorphous; performing a thermal treatment such that the first portion of the conformal semiconductor capping layer is converted from amorphous into crystalline; depositing a dielectric material over the conformal semiconductor capping layer; annealing the dielectric material, such that the conformal semiconductor capping layer is converted into a semiconductor-containing oxide layer; recessing the dielectric material and the semiconductor-containing oxide layer to form an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin and the isolation structure.