Abstract: A method including: simulating an image or characteristics thereof, using characteristics of a design layout and of a patterning process, determining deviations between the image or characteristics thereof and the design layout or characteristics thereof; aligning a metrology image obtained from a patterned substrate and the design layout based on the deviations, wherein the patterned substrate includes a pattern produced from the design layout using the patterning process; and determining a parameter of a patterned substrate from the metrology image aligned with the design layout.

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata including logic and a memory strata including memory; then performing a first placement of the logic strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the memory strata based on the first placement, where the logic includes at least one decoder representation for the memory, where the at least one decoder representation has a virtual size with width of contacts for the through silicon vias, and where the performing a first placement includes using the decoder representation instead of an actual memory decoder.

Abstract: Disclosed is an integrated circuit (IC) layout method capable of reducing an IR drop as a result of an IC layout process. The method includes the following steps: performing the IC layout process and obtaining an original IC layout; performing an IR drop analysis on the original IC layout and identifying an IR drop hot zone; determining a circuit density limit of the IR drop hot zone; and performing the IC layout process again according to the circuit density limit and obtaining an updated IC layout.

Abstract: An example is a method. A design of an integrated circuit is loaded onto an emulation system and is emulated by the emulation system. A sequence of frames is captured, by the emulation system, from the emulation. The sequence of frames includes frame intervals, and each frame interval includes a full frame and a delta primary frame subsequent to the full frame. The full frame is captured at a respective sample time, and the full frame includes signals of the design or a change of the signals relative to a respective sample time of the full frame of a previous frame interval. The delta primary frame is captured at a respective sample time, and the delta primary frame includes a change of a subset of the signals relative to a respective sample time of a previous frame of the respective frame interval. The sequence of frames is stored to memory.

Abstract: A first electronic device, electronically coupled to a second device for supplying a charge to the second electronic device, tracks the voltage requirements of the second device and dynamically adjusts its output voltage upwards or downwards to match such requirements. The second electronic device may provide feedback to the first electronic device through a feedback loop. The feedback may include an indication of the voltage requirements and/or instructions for adjusting the voltage output of the first electronic device. The second device may be, for example, a wearable audio device, while the first device is a case for the wearable audio device.

Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.

Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.

Abstract: One, two, or three test pattern generation and encoding processes are performed for a circuit design to generate compressed test patterns for one or two input channel numbers. The one, two, or three test pattern generation and encoding processes are configured to minimize active input channels for each of the compressed test patterns. A test pattern count for each of a plurality of input channel numbers is determined based on the compressed test patterns for the one or two input channel numbers, a number of active input channels for each of the compressed test patterns, and an assumption of similar input data volumes for different numbers of input channels. The test pattern count information can be employed to determine an optimal number of input channels for a test decompressor.

Abstract: The independent claims of this patent signify a concise description of embodiments. Multiple copies of the design or multiple designs are compiled into a single emulation module or prototype FPGA/sub-system to enable multiple concurrent users. The design is executed on the emulator or prototype with the main design clock always running. A debug transactor is attached to each copy of the design which connects to one software debugger per user. The improvement is especially important for long interactive debug sessions which often occur with embedded-software debug use models. This Abstract is not intended to limit the scope of the claims.

Abstract: A method, apparatus and product for hard error simulation and usage thereof. The method comprises obtaining a design of a circuit, which comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a trace of a run of a test of the circuit; and obtaining a hard error fault on a node. The method comprises determining a hard-error test coverage for the hard error fault, wherein the hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the hard error fault during an execution of the test, and wherein said determining comprises: simulating the execution of the circuit together with the hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault. An indication of the hard-error test coverage may be outputted.

Abstract: A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Abstract: Embodiments included herein are directed towards method for electronic design. Embodiments may include receiving, using at least one processor, a placed layout and one or more electronic design simulation datasets including current information associated with at least one pin. Embodiments may further include estimating a width to support the current information associated with the at least one pin and updating a pin size associated with the at least one pin based upon, at least in part, the estimated width. Embodiments may also include identifying at least one pin that is above a predetermined threshold and splitting the at least one pin that is above the predetermined threshold into a plurality of pins. Embodiments may further include generating one or more width-spacing-pattern tracks for one or more internal nets based upon, at least in part, the updated pin size.

Abstract: A method including: obtaining a characteristic of a portion of a design layout; determining a characteristic of M3D of a patterning device including or forming the portion; and training, by a computer, a neural network using training data including a sample whose feature vector includes the characteristic of the portion and whose supervisory signal includes the characteristic of the M3D. Also disclosed is a method including: obtaining a characteristic of a portion of a design layout; obtaining a characteristic of a lithographic process that uses a patterning device including or forming the portion; determining a characteristic of a result of the lithographic process; training, by a computer, a neural network using training data including a sample whose feature vector includes the characteristic of the portion and the characteristic of the lithographic process, and whose supervisory signal includes the characteristic of the result.

Abstract: According to exemplary embodiments, a system and method for automated system power supply design is provided. The system and method enables circuit designers to quickly and independently design complicated single or multi rail power supply systems including multiple loads and sequencing requirements. The power solutions offered to designers may include all required power supplies to power up the loads including sequencers and load switches. The power supply design system may be implemented on a standalone processing unit, a distributed computing network, internet based web application, or among various other network applications.

Abstract: An approach is described for a method, system, and product, the approaching includes identification of an integrated circuit design, identification of sync groups (nets having synchronous voltage levels), generation of a physical design having sync group constraints, and performance of design rule checking on a physical design based on at least transferred sync group information. This provides for performing design rule analysis at least using small minimum spacing requirements then would otherwise be required with prior techniques. In some embodiments, the approach includes a verification process that ensures that synchronous voltage behavior is appropriately associated with members of respective sync groups and cleans up old association data that is no longer relevant/correct.

Abstract: The method for creating integrated circuits (IC) protects the design of a manufactured IC from being copied or counterfeited. This method protects the design of an IC chip from deliberate copying and counterfeiting by reverse engineering to gain access to the critical points in the IC chip and to siphon its functions and design. The method makes the copying, counterfeiting, and controlling by addition of Trojan circuits during manufacturing almost impossible task. It also allows chip designers to outsource the final bonding of the tiers without any fears that their design may get compromised.

Abstract: Embodiments include a multi-level electric vehicle supply equipment (EVSE) unit. The multi-level EVSE unit can include a Level 2 charge handle, a receptacle configured to receive the Level 2 charge handle, and a Level 1 outlet including one or more plug outlets configured to receive one or more corresponding Level 1 plugs. The Level 2 charge handle can be permanently attached to the multi-level EVSE unit via a cable. The Level 1 outlet can temporarily receive the one or more corresponding Level 1 plugs. A first power meter associated with the Level 2 charge handle can meter power delivered via the Level 2 charge handle. A second power meter associated with the Level 1 outlet can meter power delivered via the Level 1 outlet. A charging logic and relay section can intelligently allocate power between the Level 2 handle and the Level 1 outlet according to charging rules.

Abstract: A method of manufacturing a semiconductor device (for a layout diagram stored on a non-transitory computer-readable medium) includes generating the layout diagram. The generating the layout diagram includes: placing standard functional cells to partially fill a logic area of the layout diagram according to at least one corresponding schematic design thereby leaving, as unfilled, a spare region in the logic area; selecting a first pitch for additional cells to be placed in the spare region, wherein use of the first pitch minimizes wasted space in the spare region; selecting standard not-yet-programmed (SNYP) spare cells, which are to become at least some of the additional cells, according to the first pitch; and placing the selected SNYP spare cells into the spare region of the layout diagram.

Abstract: Electronic design automation systems, methods, and media are presented for multi-dimension clock gate design in clock tree synthesis. In one embodiment, an input list of clock gate types is accessed, and the list is then used in generating a clock gate matrix. A circuit design with a clock tree is then accessed. The multi-dimensional design involves automatically selecting, for a first clock gate of the routing tree, a first clock gate type from the clock gate matrix based on a size and associated area for the first clock gate type to select a drive strength value for the first clock gate in the routing tree. The first clock gate is then resized to generate a resized first clock gate using the clock gate matrix to adjust a first delay value associated with the first clock gate while maintaining the drive strength value.

Abstract: In a method of manufacturing a photomask, a layout of a circuit mask pattern in a mask region corresponding to a chip region of a substrate is designed. A layout of a monitoring mask pattern representing a critical dimension (CD) of the circuit mask pattern in the mask region is designed. The monitoring mask pattern includes a mask-critical dimension uniformity (CDU) detection pattern configured to detect CDU in mask and a wafer-CDU detection pattern configured to detect CDU in wafer. A first optical proximity correction (OPC) is performed on the mask-CDU detection pattern. A second optical proximity correction is performed on the wafer-CDU detection pattern. A photomask having the circuit mask pattern and the monitoring mask pattern is formed.