Abstract: A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.

Abstract: Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.

Abstract: A method and apparatus are provided for operating a wireless power transmitter. The method includes controlling the wireless power transmitter to wirelessly transmit power for charging a first power receiver, and while transmitting the power, receiving a search signal from a second power receiver, transmitting a search response signal corresponding to the search signal, and receiving, from the second power receiver, a request join signal including at least one piece of information associated with a power requirement of the second power receiver. Based on identifying that the wireless power transmitter is capable of providing the power having an amount greater than the power requirement of the second power receiver, the method further includes transmitting a charge start command to the second power receiver.

Abstract: A vehicle is configured to be selectively connected to any one of a plurality of pieces of power equipment. The vehicle includes a power storage device, and a controller configured to control charge to the power storage device from the power equipment, and discharge from the power storage device to the power equipment. When power equipment connected to fee vehicle has been installed at a preregistered location, the controller permits discharge to that power equipment. When the power equipment connected to the vehicle has been installed at the preregistered location, the controller prohibits discharge to that power equipment unless a user performs operation of permitting discharge.

Abstract: The disclosed technology is generally directed to microcontrollers. In one example of the technology, an operating system is run on at least one processor of a multi-core controller. At the operating system, a command that is associated with a manufacturer test mode is received. A permission associated with the command is requested. The permission is based, at least in part, on the status of a one-way e-fuse. Responsive to the permission associated with the command being granted, the command is caused to be processed.

Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.

Abstract: A method for automated scan chain diagnostics includes comparing actual emission signatures for individual design elements to expected emission signatures, the individual design elements having pixels allocated thereto associated with an image of a device registered to a design layout, and determining whether the actual emission signatures differ from the expected emission signatures by more than a threshold amount to determine if a defect is present.

Abstract: A method and apparatus are provided for determining, by a wireless power transmitter, whether a wireless power receiver is removed from a wireless power network managed by the wireless power transmitter. The method includes transmitting a command signal to report power information of the wireless power receiver at stated periods; determining whether a report signal corresponding to the command signal is received from the wireless power receiver; and determining that the wireless power receiver is removed from the wireless power network, if the report signal is not received after transmitting the command signal a predetermined number of times at the stated periods.

Abstract: Methods, systems and apparatuses may provide for technology that detects, by a first monitor in a first domain of a system, a presence of a first anomaly in the first domain and encodes, by the first monitor, the presence of the first anomaly and a weight of the first anomaly into a multi-level data structure. In one example, the technology also sends, by the first monitor, the multi-level data structure to a second monitor in a second domain of the system, wherein the second domain is located at a different hierarchical level in the system than the first domain.

Abstract: A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.

Abstract: Examples described herein provide a method for designing an integrated circuit (IC) for meeting different sets of criteria. In an example, different sets of criteria are identified for an IC design. The IC design is designed to meet the different sets of criteria based on expected manufacturing variation. The IC design is caused to be manufactured as IC products. At least some of the IC products are caused to be tested. The IC products are characterized as meeting respective ones of the different sets of criteria based on testing the at least some of the IC products.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A wireless power transfer method for a wireless power transfer apparatus using full and half-bridge inverter topologies includes detecting whether or not a wireless power receiver is present within a range of power being transferrable in a wireless manner, transmitting a detection signal to the wireless power receiver, receiving at least one of identification information and setting information from the wireless power receiver, receiving a control error packet from the wireless power receiver, and controlling an amount of power to be transferred by using the combination of a driving frequency, a duty cycle or a power signal phase to the full or half-bridge inverter.

Abstract: A virtual fabrication environment for semiconductor device fabrication that determines a lowest lithography exposure dose range in which one or more defects are still reparable by deposition and etch operations is discussed. Further techniques for repairing line edge roughness caused by lithography are described.

Abstract: Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.

Abstract: Techniques include retrieving a first structural netlist (SN1) that indicates electronic components, values of programmable parameters, and connections for a first electronic circuit, and retrieving a first placed and routed netlist (PR1) that indicates physical placement of the electronic components and physical routing of connections for SN1. Also retrieved is a second structural netlist (SN2) for a different second electronic circuit. For each component in SN2, a matching component, if any, is found in SN1 based on type of component and inputs that are output from other matching components without regard to value of the programmable parameter. A different second placed and routed netlist (PR2) is generated for the second circuit by including, from PR1, all matching components and connections, updated value of the programmable parameter from SN2, and by deriving new placement and routing for non-matching components in SN2. An electronic circuit is constructed according to PR2.

Abstract: Techniques and systems for determining a route from a start point to a target point in an integrated circuit (IC) design using topology-driven line probing are described. Some embodiments can create a data structure to store a set of nodes, wherein each node is located on a horizontal probe or a vertical probe, and wherein each node has a cost. The embodiments can then perform a set of operations in an iterative loop, the set of operations comprising: selecting a lowest cost node from the set of nodes; terminating the iterative loop if the lowest cost node is located at the target point; extending a probe from the lowest cost node if the lowest cost node is not located at the target point; creating at least one new node on the probe or on an ancestor of the probe; and adding the new node to the set of nodes.

Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.

Abstract: A method includes finding, for a discretized curve comprising multiple segments, first and second segments that are closer than a threshold. The method includes determining an intersection point of the first segment and the second segment, the intersection point associated with a first parameter value for the first segment and a second parameter value for the second segment, determining an error value as a distance between a first point in the parametric curve corresponding to the first parameter value and a second point in the parametric curve corresponding to the second parameter value, and selecting the intersection point when the error value is smaller than a precision tolerance. The method includes transforming the discretized curve by removing at least a segment between the first segment and the second segment, and providing the discretized curve to manufacture a mask for reproducing the feature in the integrated circuit.

Abstract: Described is an energy share pack comprising a housing, at least one energy storage component within the housing, at least one energy conversion component within the housing, and a connection point for connecting to more than one of energy users, energy sources and other energy share packs simultaneously for sharing energy. The energy share pack may have an energy generation component for generating harvestable energy, and two or more ports of any combination of the following types: bidirectional power port, bidirectional USB port, unidirectional output power port, and unidirectional input power port. The share pack ports may operate simultaneously at different voltage levels, and at least one port may be bi-directional. Furthermore, the share packs may have an integrated display for providing information on the energy share pack in which the display is integrated and information about other energy share packs connected thereto.