Abstract: A power system applied to a handheld device including a battery, a first connecting port, a second connecting port, a first detector, a second detector, a power delivery controller, a control unit, and a switching element is provided. The first connecting port is electrically connected to the battery through a first charging path. The second connecting port is electrically connected to the battery through a second charging path. The first detector is electrically connected to the first connecting port to generate a first detection signal. The second detector is electrically connected to the second connecting port to generate a second detection signal. The control unit controls the switching element according to the first detection signal and the second detection signal to selectively electrically connect the power delivery controller to the first connecting port or the second connecting port and controls conduction statuses of the charging paths.

Abstract: An electronic device, a wireless charger and a wireless charging system are disclosed. In an embodiment an electronic device includes a metal housing including electronic components of the electronic device, a recess in the metal housing, a receiver coil configured to receive wireless power, the receiver coil located in the recess outside of the metal housing and a holding structure for the receiver coil, wherein the holding structure comprises a material with a high magnetic permeability, and wherein the receiver coil is electrically connected to the electronic components inside the metal housing.

Abstract: A solid-state thermal battery system is disclosed herein. The system includes a stationary thermal storage medium that can be charged by adding heat to the thermal storage medium. Actuated heat engines can be utilized to discharge the solid-state thermal battery, converting the heat stored in the thermal storage medium into electricity. The heat engines are actuated in a manner that reduces thermal gradients in the thermal storage medium to increase the efficiency of the system. In one embodiment, the thermal storage medium is contained in a main chamber of an insulated container. The heat engines are stored, when idle, in an ancillary chamber adjacent to the main chamber and moved into the main chamber by an actuation system to begin discharging the solid-state thermal battery. The heat engines follow a path during discharge to dynamically move between regions of the thermal storage medium to reduce thermal gradients induced therein.

Abstract: Disclosed is a battery pack including a battery module having a plurality of battery cells, and a heat dissipation member provided in contact with a bus bar at a side surface of the battery module where electrode leads of the battery cells and the bus bar coupled to the electrode leads are disposed.

Abstract: A method for accurately obtaining a photolithography parameter. In the method, photolithography is performed on a target carrier with different preset photolithography parameters by using a same mask pattern as a mask, to obtain a plurality of target patterns. Each of the target pattern is compared with a standard pattern to obtain an evaluation value, and the target pattern is set as a valid pattern, when the evaluation value corresponding to the target pattern is greater than or equal to a preset value. A Bosung curve is drawn by taking a line width of the valid pattern and a preset photolithography parameter corresponding to the line width as data. The photolithography parameter corresponding to a preset line width is obtained according to the Bosung curve.

Abstract: This application discloses a computing system implementing a design verification tool to perform functional verification on a circuit design describing an electronic device and collect samples of performance data during the functional verification. The computing system can also include a performance visualization tool to generate a profile presentation based on the samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot. The performance visualization tool can receive a data reduction request based on the performance hotspot annunciated by the profile presentation. The data reduction request can identify a subset of the performance data in the profile presentation. The performance visualization tool can generate a refined profile presentation based, at least in part, on the samples of performance data and the subset of the performance data identified in the data reduction request.

Abstract: Methods and systems that selectively controls whether a battery is electronically connected to or disconnected from operational circuitry of an electronic device are described. The switching circuitry electronically connects the battery with operational circuitry in response to external electric power being available to the operational circuitry, thereby allowing the battery to be available as a backup source of electrical power for the operational circuitry when external electric power is lost. Methods and systems also electronically disconnect the battery from the operational circuitry in response to a loss of external electric power to the operational circuitry. As a result, undesirable battery drainage is avoided if the device is left in storage or is not being used for an extended period of time.

Abstract: A reconfigurable computing platform includes a reconfigurable computing device, electro-optical transceiver, and first voltage converter disposed on a multilayer board. The electro-optical transceiver converts an optical signal at least one of to and from an electrical signal, and the electrical signal is operatively coupled to the reconfigurable computing device. The electro-optical transceiver is disposed in proximity to the reconfigurable computing device, and the first voltage converter is operatively coupled to a common voltage distributed around a periphery of the multilayer board. The first voltage converter converts the common voltage to a first operating voltage, and the first voltage converter is disposed in proximity to the reconfigurable computing device. The first operating voltage is provided to the reconfigurable computing device as a first power source.

Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.

Abstract: Methods and systems for IC photomask patterning are described. In some embodiments, a method includes inserting a dummy region in an IC design layout, the IC design layout includes an active region, and the active region and the dummy region is separated by a first distance. The method further includes performing one or more operations on the IC design layout, and the active region and the dummy region is separated by a second distance substantially less than the first distance. The method further includes performing a dummy region size reduction on the IC design layout to increase the second distance to a third distance substantially greater than the second distance, and the third distance is substantially greater than a minimum feature size to be patterned by a photolithography tool. The method further includes forming a photomask using the IC design layout.

Abstract: A method for manufacturing a semiconductor device to which corresponds a layout diagram stored on a non-transitory computer-readable medium. The method includes generating the layout diagram using an electronic design system (EDS), the EDS including at least one processor and at least one memory including computer program code for one or more programs are configured to cause the EDS to execute the generating. Testing the semiconductor device. Revising, the layout diagram, based on testing results indicative of selected standard functional cells in the layout diagram which merit modification or replacement. Programming one or more of the ECO cells which correspond to the one or more selected standard functional cells resulting in one or more programmed ECO cells. Routing the one or more programmed ECO cells correspondingly to at least one of the selected standard functional cells or to one or more other ones of the standard functional cells.

Abstract: A cell storage box for storing a battery cell includes a first end provided with a safety valve and a second end. The cell storage box includes a metal case having a bottom wall and side walls, and a thermally insulating support arranged in the metal case. The thermally insulating support includes a shoulder raised relative to the bottom wall of the metal case, a side bearing wall configured such that the cell rests against the at least one side bearing wall so as to keep the cell at a first distance from the at least one side wall of the metal case, and an opening arranged below the shoulder in order to allow smoke and gas to escape during a runaway of the cell.

Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: A method comprises obtaining device information associated with one or more computing devices, the device information comprises at least a location of each of the one or more computing devices. Based on the device information, one or more UWCFs corresponding to the one or more computing devices are adapted such that a UWCF is a sub-area of an open zone, where the open zone is an area having reflection characteristics below a reference reflection threshold. A charging rate for each of the one or more computing devices based on the one or more UWCFs is determined. A beamformed signal is then transmitted within corresponding UWCF of each of the one or more computing devices based on corresponding charging rate for wirelessly charging the one or more computing devices.

Abstract: Analyzing execution of quantum services using quantum computing devices and quantum simulators is disclosed. In one example, a classical computing device receives an operating parameter representing an operating condition of a quantum computing device. Upon determining that the operating parameter satisfies an operating environment threshold, the classical computing device initiates execution of a first instance of a quantum service on the quantum computing device. The classical computing device also simulates, using a quantum simulator, the operating condition of the quantum computing device based on the operating parameter, and executes a second instance of the quantum service using the quantum simulator under the simulated operating condition, in parallel with execution of the first instance of the quantum service. The classical computing device obtains and records a first performance characteristic of the quantum computing device and a second performance characteristic of the quantum simulator.

Abstract: A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.

Abstract: An energy storage device (ESD) manager determines charge conditions that result in charge-related aging of an energy storage device (ESD), such as a battery, cell, or the like. The ESD manager may determine charge-related costs for charge operations, which may quantify charge-related aging imposed by subjecting ESD to specified charge conditions. The ESD manager may evaluate and/or modify charge operations to reduce charge-related aging. The ESD manager may be further configured to model charge-related aging behavior over time and/or under variable charge conditions. The ESD manager may configure charge operations to ensure that charge-related performance loss remains below a threshold for a specified usage duration.

Abstract: Embodiments include a multi-level electric vehicle supply equipment (EVSE) unit. The multi-level EVSE unit can include a Level 2 charge handle, a receptacle configured to receive the Level 2 charge handle, and a Level 1 outlet including one or more plug outlets configured to receive one or more corresponding Level 1 plugs. The Level 2 charge handle can be permanently attached to the multi-level EVSE unit via a cable. The Level 1 outlet can temporarily receive the one or more corresponding Level 1 plugs. A first power meter associated with the Level 2 charge handle can meter power delivered via the Level 2 charge handle. A second power meter associated with the Level 1 outlet can meter power delivered via the Level 1 outlet. A charging logic and relay section can intelligently allocate power between the Level 2 handle and the Level 1 outlet according to charging rules.

Abstract: An inductive charger where the charging surface or coil is separated from the drive or control electronics is described.