Patents Examined by Stanetta Isaac
  • Patent number: 10431541
    Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Hui Lee, Yung-Sheng Huang, Yung-Huei Lee
  • Patent number: 10355010
    Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee
  • Patent number: 10312105
    Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-Sic Yoon, Jiung Pak, Kiseok Lee, Chan Ho Park, Hyeonok Jung
  • Patent number: 10297559
    Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
  • Patent number: 10272598
    Abstract: Anisotropic conductive film produced that a light-transmitting transfer die having openings with conductive particles disposed therein is prepared, and photopolymerizable insulating resin squeezed into openings to transfer conductive particles onto the surface of the photopolymerizable insulating resin layer, first connection layer is formed which has a structure in which conductive particles are arranged in a single layer in a plane direction of photopolymerizable insulating resin layer and the thickness of photopolymerizable insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than thickness of photopolymerizable insulating resin layer in regions in proximity to conductive particles; first connection layer is irradiated with ultraviolet rays through light-transmitting transfer die; release film is removed from first connection layer; second connection layer is formed on the surface of first connection layer opposite to light-transmitting transfer die; and th
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: April 30, 2019
    Assignee: DEXERIALS CORPORATION
    Inventors: Seiichiro Shinohara, Yasushi Akutsu
  • Patent number: 10256291
    Abstract: An object is to provide a method for manufacturing a highly reliable semiconductor device including a transistor with stable electric characteristics. A method for manufacturing a semiconductor device includes the steps of: forming a gate electrode over a substrate having an insulating surface; forming a gate insulating film over the gate electrode; forming an oxide semiconductor film over the gate insulating film; irradiating the oxide semiconductor film with an electromagnetic wave such as a microwave or a high frequency; forming a source electrode and a drain electrode over the oxide semiconductor film irradiated with the electromagnetic wave; and forming an oxide insulating film, which is in contact with part of the oxide semiconductor film, over the gate insulating film, the oxide semiconductor film, the source electrode, and the drain electrode.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akiharu Miyanaga
  • Patent number: 10256142
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: April 9, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 10236282
    Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Kimin Jun, Il-Seok Son, Rajashree Baskaran, Paul B. Fischer
  • Patent number: 10211102
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a core region and a peripheral region, and prior to forming a metal silicide in the core region, forming a sidewall layer on opposite sides of a gate structure of a core region device. The sidewall layer includes sequentially, from the inside out, a silicon oxide layer, a first silicon nitride layer, a first silicon nitride layer, a second silicon oxide layer, and a second silicon nitride layer, or the sidewall layer includes, from inside out, a first silicon nitride layer and a second silicon nitride layer. The sidewall layer having such structure ensures that the formed metal silicide has a good morphology in the core region to achieve good device performance.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: February 19, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jinshuang Zhang, Shengfen Chiu
  • Patent number: 10204902
    Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hae-Wang Lee
  • Patent number: 10204903
    Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. A plurality of fin structures are formed in the substrate. The fin structures include an upper part and a lower part. An isolation layer is formed on the substrate. The lower part of the plurality of fin structures is embedded in the isolation layer. A source including a first source portion and a second source portion is formed in a first side of the substrate. The first source portion partially occupies the fin structures along a length direction. The second source portion is formed over the first source portion. The second source portion elevates the fin structures. A drain is formed in a second side of the substrate. A distance between the source to the drain defines a channel region. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the elevated fin structures and channel region.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ping Zheng, Eng Huat Toh
  • Patent number: 10199341
    Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang
  • Patent number: 10199464
    Abstract: Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-? gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Cheng Chi, Chi-Chun Liu, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10192836
    Abstract: A semiconductor device equipped with a base board, a first element, a second element, and an interposer board, wherein: the first element is positioned on the base board; a signal transmitting/receiving terminal of the first element and a plurality of base board terminals contact one another; the second element is positioned on the base board; a signal transmitting/receiving terminal of the second element and the plurality of base board terminals contact one another; the interposer board is positioned so as to extend on the first element and the second element; a first contactless signal transmitting/receiving unit of the interposer board is capable of contactlessly transmitting and receiving a signal; and a second contactless signal transmitting/receiving unit of the interposer board is capable of contactlessly transmitting and receiving a signal.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 29, 2019
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito
  • Patent number: 10181477
    Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hirokazu Ishigaki, Tatsuya Okamoto, Masao Shingu
  • Patent number: 10177278
    Abstract: A semiconductor light emitting device includes: a multilayer semiconductor body having a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, an active layer between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, and at least one recess exposing the first conductivity-type semiconductor layer, and an insulating part on an internal sidewall of the at least one recess and an upper surface of the second conductivity-type semiconductor layer. The insulating part has an insulating spacer on the internal sidewall of the recess, and a lateral surface of the insulating spacer has a surface without an angular point from an upper end to a lower end thereof.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Hyun Kim, Jae Ryung Yoo, Gi Bum Kim, Ha Yeong Son, Sang Seok Lee
  • Patent number: 10163681
    Abstract: A method for bonding of a first solid substrate to a second solid substrate which contains a first material with the following steps, especially the following sequence: formation or application of a function layer which contains a second material to the second solid substrate, making contact of the first solid substrate with the second solid substrate on the function layer, pressing together the solid substrates for forming a permanent bond between the first and second solid substrate, at least partially reinforced by solid diffusion and/or phase transformation of the first material with the second material, an increase of volume on the function layer being caused.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: December 25, 2018
    Assignee: EV Group E. Thallner GmbH
    Inventors: Klaus Martinschitz, Markus Wimplinger, Bernhard Rebhan, Kurt Hingerl
  • Patent number: 10153274
    Abstract: A p-type well is formed in a semiconductor substrate, and an n+-type semiconductor region and a p+-type semiconductor region are formed in the p-type well to be spaced apart from each other. The n+-type semiconductor region is an emitter semiconductor region of a bipolar transistor, and the p-type well and the p+-type semiconductor region are base semiconductor regions of the bipolar transistor. An electrode is formed on an element isolation region between the n+-type semiconductor region and the p+-type semiconductor region, and at least apart of the electrode is buried in a trench which is formed in the element isolation region. The electrode is electrically connected to the n+-type semiconductor region.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Sadayuki Ohnishi
  • Patent number: 10153362
    Abstract: In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: December 11, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10141456
    Abstract: The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: November 27, 2018
    Assignee: Fraunhofer Gesellschaft Zur Forderung Der Angew. Forschung E.V.
    Inventors: Andreas Hürner, Tobias Erlbacher