Abstract: In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.

Abstract: The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas.

Abstract: A lighting device is provided. The lighting device includes a lightguide panel having an end face and a light-emitting device configured to emit light toward the end face of the lightguide panel. The light-emitting device includes a light-emitting element and a first light-transmissive member provided between the end face of the lightguide panel and the light-emitting element. The first light-transmissive member has a plurality of protrusions on a surface thereof. At least one of the plurality of protrusions is in contact with the end face of the lightguide panel.

Abstract: Provided is an organic light emitting diode including a first electrode layer, a second electrode layer opposing the first electrode layer, a first light emitting layer between the first and second electrode layers to generate a first light having a first wavelength, a second light emitting layer between the first light emitting layer and the second electrode layer to generate a second light having a second wavelength which is longer than the first wavelength, and a charge generating layer between the first and second light emitting layers. The first and second lights are emitted through the second electrode layer. An optical length between the first and second electrode layers is substantially the same as a fourth resonant distance of the first light.

Abstract: Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package stiffener may also be coupled with the adhesive adjacent to the die. A magnetic thin film may be coupled with the package stiffener. Other embodiments may be described and/or claimed.

Abstract: In a representative embodiment, an apparatus, comprises a substrate; a microelectronic ultrasonic transducer (MUT) disposed over the substrate; and a thermoelectric device disposed proximate to the MUT and configured to provide heat to or remove heat from the MUT. A microelectromechanical MEMs device is also described.

Abstract: There is provided a method for manufacturing a semiconductor light emitting device package including steps of disposing a plurality of light emitting structures on a support substrate, each light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, shaping a mixture containing a wavelength conversion material and a glass composition on the plurality of light emitting structures, sintering the mixture to form a wavelength conversion part, removing the support substrate, and cutting the plurality of light emitting structures into individual device units.

Abstract: A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer thereon in the gate trench; forming a first tungsten (W) layer on a surface of the metal gate layer, and forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions; and filling with W through an atomic layer deposition (ALD) process. The blocking layer prevents ions in the precursors from aggregating on an interface and penetrating into the metal gate layer and the gate dielectric layer. At the same time, adhesion of W is enhanced, a process window of W during planarization is increased, reliability of the device is improved and the gate resistance is further reduced.

Abstract: A workpiece has a plurality of low-dielectric-constant insulation films and a metallic pattern stacked on a surface of a semiconductor substrate. Devices are formed in a plurality of regions partitioned by streets formed in a grid pattern. Surfaces of the devices formed on the workpiece are covered with a surface protective member, leaving the streets exposed. A dispersion of abrasive grains in an etching liquid capable of dissolving the metallic pattern is blasted against the workpiece together with compressed gas so as to remove the low-dielectric-constant insulation films and the metallic pattern on the streets, thereby exposing the semiconductor substrate. The workpiece is divided with the semiconductor substrate exposed by the wet blasting step subjected to dry etching so as to divide the workpiece along the streets.

Abstract: A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a second region, wherein the first region and the second region have a preset distance; forming a well area in the substrate; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and a second supporting gate crossing the second fin portion; forming a dielectric layer on the well area; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and a second conductive structure connecting to the second fin portion.

Abstract: A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled.

Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

Abstract: Methods for forming a multi-threshold voltage device on a substrate are provided herein. In some embodiments, the method of forming a multi-threshold voltage device may include (a) providing a substrate having a first layer disposed thereon, wherein the substrate comprises a first feature and a second feature disposed within the first layer; (b) depositing a blocking layer atop the substrate; (c) selectively removing a portion of the blocking layer from atop the substrate to expose the first feature; (d) selectively depositing a first work function layer atop the first feature; (e) removing a remainder of the blocking layer to expose the second feature; and (f) depositing a second work function layer atop the first work function layer and the second feature.

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

Abstract: The present disclosure controls the heat source unit such that a to-be-processed object in which a hydrogen-containing to-be-processed layer is formed is irradiated with light in two stages, and thus the electrical characteristics of a semiconductor device may be suppressed and prevented from being deteriorated due to hydrogen. That is, ultraviolet light (UV) which is firstly radiated may induce a chemical reaction for separating Si—H bonds in the to-be-processed layer, and infrared light (IR) which is secondly radiated may induce a thermal reaction for vaporizing the separated hydrogen from the Si—H bonds. As such, both a chemical reaction for separating bonds of hydrogen and other ions in the to-be-processed layer and a thermal reaction for vaporizing hydrogen are performed, and thus hydrogen may be more easily removed than a temperature at which hydrogen is vaporized from the to-be-processed layer by only a thermal reaction.

Abstract: The present invention provides a method for producing a back-contact back-sheet for a photovoltaic module comprising back-contact cells. The method comprising providing a substrate (210) having an outer surface (210os) facing the air-side of the photovoltaic module and an inner surface (210is) opposite the outer surface (210os) and facing the inside of the photovoltaic module. A layer of electrically conductive material (220) adapted to be formed as a connecting circuit (220c) to the electrodes of the solar cells is then applied to the substrate (210). The application of the layer of electrically conductive material (220) to the substrate (210) is performed in such a way that the layer of electrically conductive material (220) fixedly adheres to the inner surface (210is) of the substrate (210). The layer of electrically conductive material (220) is then processed so as to form the connecting circuit (220c).

Abstract: A nanostructured chip includes a substrate and a nanostructured layer, wherein the substrate has a first surface and a second surface on which the nanostructured layer is formed. A method of producing the nanostructured chip includes the step of forming the nanostructured layer on the second surface of the substrate. Whereby, the nanostructured layer effectively disperses a stress to increase the flexural strength of the nanostructured chip. Therefore, during the subsequent procedures to form an epitaxial layer on the first surface, the nanostructured layer is helpful to prevent the epitaxial layer from generating cracks, and prevent the substrate from bowings, or fragments.

Abstract: The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain regions and epitaxial grown channel regions. An epitaxially grown diffusion barrier layer separates the epitaxial grown channel regions from underlying deep n-wells and p-wells. The epitaxial source/drain regions allow for a low thermal budget that in combination with the diffusion barrier layer allows the deep n-wells and p-wells to be heavily doped while preserving high purity in the channel layers.

Abstract: According to one embodiment, a magnetic element includes a first stacked unit and a third ferromagnetic layer. The first stacked unit includes first and second ferromagnetic layers, and a first non-magnetic layer. The first ferromagnetic layer has a first magnetization. The second ferromagnetic layer is separated from the first ferromagnetic layer in a first direction, and has a second magnetization. The first non-magnetic layer is provided between the first and second ferromagnetic layers. The third ferromagnetic layer is stacked with the first stacked unit in the first direction, and has a third magnetization. 2?NzMs is not less than 0.9 times of a magnetic resonance frequency (Hz) of the third ferromagnetic layer, when the second magnetization is Ms (emu/cc), a demagnetizing coefficient of the second ferromagnetic layer is Nz, and a gyro magnetic constant is ? (Hz/Oe).

Abstract: An image sensor is described. The image sensor may include a substrate including a pixel area, a logic area, and a guard area disposed between the pixel area and the logic area. The guard area may substantially prevent transfer of heat generated in the logic area from reaching the pixel area.