Abstract: A semiconductor device includes a P-type semiconductor substrate including a pad, a ground pad, and a power supply pad, a first N-type diffusion region formed on the P-type semiconductor substrate and connected to the pad, an internal circuit region formed on the P-type semiconductor substrate, and a minority carrier capture region formed between the first N-type diffusion region and the internal circuit region for capturing minority carriers in the P-type semiconductor substrate caused by a surge to the pad. The minority carrier capture region has a triple guard ring including a first P-type diffusion region, a second P-type diffusion region, and a second N-type diffusion region located between the first P-type diffusion region and the second P-type diffusion region. Each of the first P-type diffusion region and the second P-type diffusion region is connected to the ground pad respectively through metal film wirings that are separately formed.

Abstract: This semiconductor device (100) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed on the gate insulating layer (4) and which includes a first conductor region (55) and a first semiconductor region (51) that overlaps at least partially with the gate electrode (3) with the gate insulating layer (4) interposed between them; a source electrode (6s) formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50); a drain electrode (6d) which is formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50) and which is electrically connected to the first conductor region (55); and a conductive layer (60) which is formed in contact with the upper surface of the oxide layer (50) and which a plurality of holes (66) or notches.

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract: Provided are organic luminescence display and method for manufacturing the same. According to an aspect of the present invention, there is provided an organic luminescence display comprising a substrate and a plurality of pixels disposed on the substrate. The pixels comprise a plurality of first pixels, each comprising a first organic light-emitting layer, and a plurality of second pixels which are smaller than the first pixels and each of which comprises a second organic light-emitting layer. The surface roughness of the second organic light-emitting layer is greater than the surface roughness of the first organic light-emitting layer.

Abstract: An organic light emitting display device includes a first electrode, a second electrode facing the first electrode, an organic light emitting layer disposed between the first and second electrodes, a first auxiliary structure and a second auxiliary structure both of which are disposed between the first and second electrodes. The first electrode is disposed on a substrate having a first sub-pixel region, a second sub-pixel region and a third sub-pixel region. The organic light emitting layer includes a first organic light emitting layer, a second organic light emitting layer and a third organic light emitting layer. The first auxiliary structure includes a first doping pattern, a first resonance auxiliary pattern, a second doping pattern and a second resonance auxiliary pattern. The second auxiliary structure includes a third doping pattern, a third resonance auxiliary pattern, a fourth doping pattern and a fourth resonance auxiliary pattern.

Abstract: Disclosed is an organic light-emitting display device capable of preventing the occurrence of cracks at corner regions of an adhesive layer. The organic light-emitting display device includes a first substrate including a plurality of pixels and a second substrate. A thin film transistor (TFT) located at each pixel of the first substrate. A pixel electrode is also located at each pixel. An organic light-emitting unit that emits light is coupled to each pixel electrode. A common electrode is electrically coupled to each organic light-emitting unit. An adhesive layer is coupled to the common electrode. The adhesive layer attaches the first and second substrates. The corner regions of the adhesive layer are rounded in order to control the creation of cracks in the adhesive layer and thereby prevent moisture from entering the active area of the device.

Abstract: A method for manufacturing a sloped structure is disclosed. The method includes the steps of: (a) forming a sacrificial film above a substrate; (b) forming a first film above the sacrificial film, the first film having a first portion connected to the substrate, a second portion located above the sacrificial film, a third portion located between the first portion and the second portion, and a thin region in a portion of the third portion or in a boundary section between the second portion and the third portion and having a thickness smaller than the first portion; (c) removing the sacrificial film; and (d) bending the first film in the thin region, after the step (c), thereby sloping the second portion of the first film with respect to the substrate.

Abstract: A semiconductor device includes a plurality of gate structures on a substrate, the plurality of gate structures including a gate metal pattern and delimiting air gaps formed therebetween, an insulating layer on the plurality of gate structures, and a porous insulating layer between the plurality of gate structures and the insulating layer, the porous insulating layer configured to cross the plurality of gate structures to delimit the air gaps.

Abstract: An array of color filter elements may be formed over an array of photodiodes in an integrated circuit for an imaging device using a carrier substrate. The carrier substrate may have a planar surface with a release layer. A layer of color filter material may be applied to the release layer. The carrier substrate may then be flipped and the layer of color filter material may be bonded to the integrated circuit. Heat may be applied to activate the release layer and the carrier substrate may be removed at the interface between the release layer and the color filter material. The layer of color filter material may be patterned either before bonding the layer of color filter material or after the carrier substrate is removed. A layer of microlenses may be formed over the array of color filter elements using a carrier substrate.

Abstract: A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate.

Abstract: A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section.

Abstract: A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.

Abstract: A Schottky diode includes a device structure having a central portion and a plurality of fingers. Distal portions of the fingers overlie leakage current control (LCC) regions. An LCC region is relatively narrow and deep, terminating in proximity to a buried layer of like polarity. Under reverse bias, depletion regions forming in an active region lying between the buried layer and the LCC regions occupy the entire extent of the active region and thereby provide a carrier depleted wall. An analogous depletion region occurs in the active region residing between any pair of adjacent fingers. If the fingers include latitudinal oriented fingers and longitudinal oriented fingers, depletion region blockades in three different orthogonal orientations may occur. The formation of the LCC regions may include the use of a high dose, low energy phosphorous implant using an LCC implant mask and the isolation structures as an additional hard mask.

Abstract: In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region.

Abstract: A microelectronic device includes a substrate having at least one microelectronic component on a surface thereof, a conductive via electrode extending through the substrate, and a stress relief structure including a gap region therein extending into the surface of the substrate between the via electrode and the microelectronic component. The stress relief structure is spaced apart from the conductive via such that a portion of the substrate extends therebetween. Related devices and fabrication methods are also discussed.

Abstract: The present disclosure provides a means to build a solar cell that is transparent to and polarizes visible light, and to transfer the energy thus generated to electrical power wires.

Abstract: A nitride semiconductor light-emitting element includes a layered semiconductor body which is made of a group III nitride semiconductor, and includes a light-emitting facet, and a multilayer protective film which is formed to cover the light-emitting facet of the layered semiconductor body, and includes a plurality of insulating films. The multilayer protective film includes a first protective film and a second protective film covering the first protective film. The first protective film is a crystalline film which is made of nitride containing aluminum, and is at least partially crystallized. The second protective film is a crystalline film which is made of oxide containing aluminum, and is at least partially crystallized.

Abstract: A method of directly growing graphene of a graphene-layered structure, the method including ion-implanting at least one ion of a nitrogen ion and an oxygen ion on a surface of a silicon carbide (SiC) thin film to form an ion implantation layer in the SiC thin film; and heat treating the SiC thin film with the ion implantation layer formed therein to graphenize a SiC surface layer existing on the ion implantation layer.

Abstract: A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region.

Abstract: Various methods and devices that involve radio frequency (RF) switches with clamped bodies are provided. An exemplary RF switch with a clamped body comprises a channel that separates a source and a drain. The RF switch also comprises a clamp region that spans the channel, extends into the source and drain, and has a lower dopant concentration than both the source and drain. The RF switch also comprises a pair of matching silicide regions formed on either side of the channel and in contact with the clamp region. The clamp region forms a pair of Schottky diode barriers with the pair of matching silicide regions. The RF switch can operate in a plurality of operating modes. The pair of Schottky diode barriers provide a constant sink for accumulated charge in the clamped body that is independent of the operating mode in which the RF switch is operating.