Patents Examined by Stephen Elmore
  • Patent number: 10001928
    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided, wherein the memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: loading at least one first address information of at least one first logical-physical mapping table from the rewritable non-volatile memory module to a first buffer area when the memory storage device is operated in a first mode, wherein the first address information has a first data quantity; and loading at least one second address information of at least one second logical-physical mapping table from the rewritable non-volatile memory module to the first buffer area when the memory storage device is operated in a second mode, wherein the second address information has a second data quantity, and the first data quantity is less than the second data quantity.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: June 19, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10001942
    Abstract: Techniques are provided for asynchronous semi-inline deduplication. A multi-tiered storage arrangement comprises a first storage tier, a second storage tier, etc. An in-memory change log of data recently written to the first storage tier is evaluate to identify a fingerprint of a data block recently written to the first storage tier. A donor data store, comprising fingerprints of data blocks already stored within the first storage tier, is queried using the fingerprint. If the fingerprint is found, then deduplication is performed for the data block to create deduplicated data based upon a potential donor data block within the first storage tier. The deduplicated data is moved from the first storage tier to the second storage tier, such as in response to a determination that the deduplicated data has not been recently accessed. The deduplication is performed before cold data is moved from first storage tier to second storage tier.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 19, 2018
    Assignee: NetApp Inc.
    Inventors: Alok Sharma, Girish Hebbale Venkata Subbaiah, Kartik Rathnakar, Venkateswarlu Tella, Mukul Sharma
  • Patent number: 9983793
    Abstract: Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: May 29, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lei Liu, Chengyong Wu, Xiaobing Feng
  • Patent number: 9983833
    Abstract: A method of updating a file in a solid state drive (SSD) and an SSD configured to update a file in the SSD is disclosed. In one embodiment, the method includes performing one or more writes to a holding file in an auxiliary memory, the one or more writes corresponding to an update for a target file in the auxiliary memory. The method further includes applying the update to the target file in the auxiliary memory when each of the one or more writes has been successfully written to the holding file, and resetting the holding file when less than all of the one or more writes have been successfully written to the holding file. In one embodiment, a flash controller in communication with the auxiliary memory performs the update.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: May 29, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Gordon W. Waidhofer, Ali Aiouaz, Christopher S. Delaney, Leland W. Thompson
  • Patent number: 9971707
    Abstract: A system is described to provide protection key access control in a system whose operating system and processor were not designed to provide a protection key memory access control mechanism. Such a system can be applied to an emulator or to enable a system that executes native applications to be interoperable with a legacy system that employs protection key memory access control.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 15, 2018
    Assignee: LZLABS GMBH
    Inventor: Jan Jaeger
  • Patent number: 9967342
    Abstract: A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: May 8, 2018
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John D. Davis, John Hayes
  • Patent number: 9946485
    Abstract: A changed block bitmap of a volume of storage is represented by a data marker that includes an offset to a first dirty block and an offset to a last dirty block. The blocks between the first and last dirty blocks are represented by contiguous clean block identifiers, contiguous dirty block identifiers, and contiguous mixed clean and dirty block identifiers. The contiguous clean block identifiers and contiguous dirty block identifiers use one or two bits to indicate identifier type. The remaining bits indicate a numerical count of contiguous clean or dirty blocks. The contiguous mixed clean and dirty block identifiers may use one bit per block to indicate change status. The data marker may be smaller than a corresponding changed block bitmap.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 17, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Arieh Don, Slavik Neymer, Jehuda Shemer, Alexandra Solan, Valerie Lotosh
  • Patent number: 9946496
    Abstract: A computing system includes a storage device and a host. The storage device includes a volatile memory and a non-volatile memory, and is configured to receive data for storage in the non-volatile memory, to buffer at least some of the received data temporarily in the volatile memory, and to guarantee that any data, which is not part of a predefined amount of data that was most recently received, has been committed to the non-volatile memory. The host is configured to send the data for storage in the storage device, and, in response to a need to commit given data to the non-volatile memory, to send the given data to the storage device followed by at least the predefined amount of additional data.
    Type: Grant
    Filed: March 20, 2016
    Date of Patent: April 17, 2018
    Assignee: Elastifile Ltd.
    Inventors: Eyal Lotem, Avraham Meir, Shahar Frank
  • Patent number: 9946489
    Abstract: A method of indirection replay for a flash storage system includes writing data, in a host stream, to blocksets of the flash storage system. The host blocksets are assigned a major sequence number incremented from the most recently closed host blockset. The method includes writing an indirection journal to each host blockset which are associated with the assigned major sequence number. The method includes writing data, in a garbage collection (GC) stream, to other blocksets of the flash storage system. The GC blocksets are assigned a major sequence number, based on the most recently closed host blockset, and a minor sequence number, incremented from the most recently closed GC blockset. The method includes writing an indirection journal to each GC blockset which are associated with the assigned major and minor sequence numbers. The indirection table is constructed by replaying the journals of the blocksets in order of major sequence and minor sequence numbers.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: April 17, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: David George Dreyer, Colin Christopher McCambridge, Phillip Peterson, Sanjay Subbarao
  • Patent number: 9940043
    Abstract: Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection logic, a media management component is selected to manage the storage operation. In response to the initiation of a storage operation and according to a second set of selection logic, a network storage device to associate with the storage operation. The selected media management component and the selected network storage device perform the storage operation on the electronic data.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 10, 2018
    Assignee: Commvault Systems, Inc.
    Inventors: Rajiv Kottomtharayil, Parag Gokhale, Anand Prahlad, Manoj Kumar Vijayan, David Ngo, Varghese Devassy
  • Patent number: 9933964
    Abstract: According to certain aspects, a system can include a client computing device configured to: in response to user interaction, store an identifier associated with a first tag in association with a first file; and in response to instructions to perform a secondary copy operation, forward the first file, a second file, and the identifier associated with the first tag. The system may also include a secondary storage controller computer(s) configured to: based on a review of the identifier associated with the first tag, identify the first file as having been tagged with the first tag; electronically obtain rules associated with the first tag; perform on the first file at least a first secondary storage operation specified by the rules associated with the first tag; and perform on the second file at least a second secondary storage operation, wherein the first and second secondary storage operations are different.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 3, 2018
    Assignee: Commvault Systems, Inc.
    Inventors: Manas Bhikchand Mutha, Pavan Kumar Reddy Bedadala, Vinit Dilip Dhatrak, Christopher A. Alonzo
  • Patent number: 9934151
    Abstract: A method and information handling system configured to executing instructions of an SSD dynamic optimization buffer switching system and configured to detecting SSD storage capacity utilization via an SSD controller. The method and information handling system further configured to reallocate buffer capacity from write acceleration buffer capacity to garbage collection buffer capacity to increase buffer availability for garbage collection when SSD storage capacity utilization exceeds a threshold level.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 3, 2018
    Assignee: Dell Products, LP
    Inventor: Lip Vui Kan
  • Patent number: 9933945
    Abstract: Techniques for shrinking a filesystem backed by a volume identify slices in the volume to be evacuated in order to reach a target size, identify a target endpoint in the volume, and evacuate identified slices to available locations prior to the target endpoint. The same data is typically not moved from slice to slice multiple times.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 3, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Qi Mao, Jean-Pierre Bono, Ahsan Rashid, Xianlong Liu, Chang Yong Yu, Ruiling Dou, Alexander Mathews, Henry Fang, Gyanesh Kumar Choudhary
  • Patent number: 9934089
    Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 3, 2018
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, John Colgrove, John D. Davis
  • Patent number: 9928006
    Abstract: A memory device may include an input/output control unit for receiving input signals through an input/output bus, and a control logic unit for receiving control signals, and when the control signals satisfy first through fourth conditions, the control logic unit identifies a command, an address, data and an identifier of the memory device in the input signals, and latches the input signals. The fourth condition is different from the first through third conditions.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Bum Kim, Dong-Ku Kang
  • Patent number: 9928186
    Abstract: A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 27, 2018
    Assignee: Netlist, Inc.
    Inventors: Hyun Lee, Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
  • Patent number: 9921775
    Abstract: A method of managing memory of a control plane for services in a computer system that includes executing a service host process of the control plane on a software platform of the computer system, the service host process including runtime software configured to manage lifecycles of objects representing the services, the objects being associated with the service host process and being marked as available; determining an amount of memory in the computer system consumed by the objects; marking a plurality of the objects as paused in response to the amount of memory consumed by the objects exceeding a threshold; storing at least a portion of a runtime context of each of the plurality of objects in storage of the computer system; and disassociating the plurality of objects from the service host process to reclaim memory consumed by the objects.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 20, 2018
    Assignee: VMware, Inc.
    Inventors: Georgios Chrysanthakopoulos, Pieter Noordhuis
  • Patent number: 9916256
    Abstract: A method of accessing a persistent memory over a memory interface is disclosed. In one embodiment, the method includes allocating a virtual address range comprising virtual memory pages to be associated with physical pages of a memory buffer and marking each page table entry associated with the virtual address range as not having a corresponding one of the physical pages of the memory buffer. The method further includes generating a page fault when one or more of the virtual memory pages within the virtual address range is accessed and mapping page table entries of the virtual memory pages to the physical pages of the memory buffer. The method further includes transferring data between a physical page of the persistent memory and one of the physical pages of the memory buffer mapped to a corresponding one of the virtual memory pages.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: March 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: David Stanley Maxey, Nidish Ramachandra Kamath, Vikas Kumar Agrawal
  • Patent number: 9916088
    Abstract: A memory system includes a memory device including a plurality of memory blocks, wherein each of the plurality of memory blocks includes a plurality of pages, wherein each of the plurality of pages includes a plurality of memory cells electrically coupled to a plurality of word lines, wherein read data and write data requested from a host are stored in the plurality of memory cells; and a controller configured to (i) program first data corresponding to a write command/read command received from the host in a first page of a first memory block selected among the plurality of memory blocks (ii) record position information of second data in the first page, and (iii) program the second data in a second page next to the first page in the first memory block.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: March 13, 2018
    Assignee: SK Hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 9910783
    Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair