Abstract: A write method and a write apparatus for a storage device, where the write method includes: acquiring n numerical values that need to be written; determining n bits corresponding to the n numerical values, and information about a stuck-at fault included in the n bits; grouping the n bits into B groups of bits, so that the B groups of bits meet a grouping condition; and correspondingly writing the n numerical values according to information about a stuck-at fault included in each group of bits in the B groups of bits and a numerical value that needs to be written and that is corresponding to the information about the stuck-at fault included in each group of bits in the B groups of bits.

Abstract: Various embodiments of a system and method for securely caching and sharing image data. A process can generate image data and store the image data into the protected cache using a UUID that is cryptographically derived from the image data. Any process with access to the UUID may retrieve the image data. Because the UUID is uniquely derived from the actual data of the generated file, a process will only be able to retrieve image data that could have been generated by a process associated with the user account, or from a process associated with a user account that could have generated the image data, or that otherwise has a record of the image data.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to process data to form codewords and to send the codewords to the memory to be stored at locations of the memory that are restricted based on a non-adjacency pattern.

Abstract: Disclosed is a method of selecting a data candidate having a maximum value from a plurality of data candidates stored in columns in a memory array. The method includes computing marker bit values for each row of data in the memory array, and performing a Boolean OR operation on the marker bit values to generate a responder signal value. Also disclosed is a memory device including a memory array of memory cells arranged in rows and columns, and responder signal circuitry to generate a responder signal responsive to positive identification of a data candidate in the memory array.

Abstract: A system includes non-volatile memory storing firmware and an embedded baseboard management controller (BMC). The BMC includes a BMC volatile memory and a BMC processor coupled to the BMC volatile memory and the non-volatile memory. The BMC processor performs a first method wherein the firmware is obtained from the non-volatile memory, instrumented, and stored on a host computer volatile memory. Also in the first method, separate copies of vital debug information about the instrumented firmware are stored on the BMC volatile memory and the host computer volatile memory. The system further includes a host computer housing the embedded BMC, the host computer volatile memory, and a host computer processor coupled to the host computer volatile memory. The host computer processor performs a second method wherein the instrumented firmware is obtained from the host computer volatile memory and executed.

Abstract: Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.

Abstract: A storage system includes data storage devices, bus conductors, and mobile reader/writer devices. Each of the storage devices is positioned between insulators, is at one of a plurality of locations on one of one or more shelf assemblies, and comprises a processor coupled to a memory and an interface device. One of the bus conductors is adjacent each of the insulators. Each of the reader/writer devices includes a transport apparatus, a processor and a memory. The transport apparatus is configured to move one of the reader/writer devices to one or more of the locations when engaged. The processor is coupled to the transport apparatus and the memory and is configured to execute machine executable code to: engage the transport apparatus to position one of the reader/writer devices to one of the locations in response to a received operation; couple power to one of the storage devices; and execute the operation.

Abstract: Various exemplary embodiments relate to a system for hashing a value into a cache, the system including a processor for performing a series of instructions; a memory; and the cache including a plurality of slots, each slot including two locations to store values, each location comprising a tag value and an index, the cache in communication with the memory and the processor, the cache configured to calculate a target slot in the cache for an object, determine if a location is available, store a characteristic of the object in the index of the location, and update the tag value of the location.

Abstract: A processor generates stream information indicating a stream of access on the basis of the positional relationship on a storage device among a plurality of accessed first data blocks. The processor associates sequence information representing the positional relationship on the storage device with a plurality of second data blocks prefetched in a memory on the basis of the stream information. When a certain second data block is accessed, the processor searches for another second data block that is determined to be earlier in the order of access made by the stream than the certain second data block, on the basis of the sequence information. The processor removes the found second data block from the memory.

Abstract: A storage apparatus includes: a first storage device that stores data; a proxy storage processor that records first data in the first storage device in a power-off state of a second storage device, while a writing destination of the first data is the second storage device, and moves the first data to the second storage device after the second power storage is powered on, while the first data is recorded in the first storage device; and a cache releaser that deletes the first data from a cache memory after the proxy storage processor stores the first data in the second storage device, while the first data is recorded in the first storage device, so that it is possible to efficiently use the cache memory.

Abstract: Technologies are generally described for systems, devices and methods effective to utilize a solid state memory device. A memory device may include one or more input/output ports effective to receive data at, and facilitate transfer from, the memory device. The memory device may further include a memory controller. The memory controller may be effective to control access to data stored in the memory device. The memory device may further include two or more flash chips effective to store data in the memory device. The memory device may further include a crossbar switch. The crossbar switch may be coupled between the one or more input/output ports and the two or more flash chips. The crossbar switch may be effective to enable the one or more input/output ports to access the two or more flash chips through the memory controller.

Abstract: A storage controller that improves performance of a storage device by reducing the number of data I/O operations. The storage controller, as part of a storage device and a storage system, and in a method of operating the storage controller, includes a host interface receiving data requested for storage from a host and lifetime information indicating a change period of the data, and a data placement manager determining a storage position of the data in a flash memory based on the lifetime information of the data.

Abstract: A circuit includes a Virtually Indexed Physically Tagged (VIPT) cache and a cache coherency circuit. The VIPT cache includes a plurality of sets and performs a memory operation by selecting, using a Virtual Set Address (VSA), a first tag of a first set. The cache coherency circuit is to detect cache aliasing during memory operations of the VIPT cache when a second tag maps a physical address to a second set of the VIPT cache, the second set being different than the first set. A method of managing a VIPT cache includes performing, by the VIPT cache, a memory operation and determining, using a cache coherency protocol, that cache aliasing has occurred during the memory operation.

Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.

Abstract: A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data.

Abstract: The invention introduces a method for dynamic partitioning, performed by a processing unit, including at least the following steps. A storage-unit ID (identifier) associated with a storage unit is acquired, where the storage unit is coupled to the processing unit. Parameters corresponding to the storage-unit ID are obtained and the length of a physical super-page is calculated according to the parameters. The length of a data buffer is obtained and the quantity of logical partitions is calculated according to the length of the physical super-page and the length of the data buffer. The quantity of logical partitions is stored in a DRAM (Dynamic Random Access Memory).

Abstract: A data storage device includes a memory (including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion), a plurality of data latches, and routing circuitry coupled to the plurality of data latches. The routing circuitry is configured to cause write data, received from a controller, to be stored at a data latch of the plurality of data latches. The routing circuitry is further configured to cause the write data to be copied from the data latch to a particular portion of the memory based on receiving a program mode command after the write data is stored at the data latch, where the program mode command indicates the particular portion as one of the SLC memory portion or the MLC memory portion.

Abstract: Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.

Abstract: A plurality of storage nodes cooperating as a storage cluster is provided. Each of the plurality of storage nodes has storage memory. Each storage node of the plurality of storage nodes is configurable to direct erasure coded striping of data of one of an Mode or data segment across the plurality of storage nodes of the storage cluster, with at least one storage node of the plurality of storage nodes having a differing amount of storage capacity of the storage memory from an amount of storage capacity of another storage node in the plurality of storage nodes. A method of storing data in a storage cluster is also provided.

Abstract: A cache memory stores 2^J-byte cache lines and includes an array of 2^N sets each holding tags each X bits, an input receives a Q-bit memory address, MA[(Q?1):0], having: a tag MA[(Q?1):(Q?X)] and an index MA[(Q?X?1):J]. Q is an integer at least (N+J+X?1). In a first mode: set selection logic selects one set using the index and LSB of the tag; comparison logic compares all but LSB of the tag with all but LSB of each tag in the selected set and indicates a hit if a match; otherwise allocation logic allocates into the selected set. In a second mode: the set selection logic selects two sets using the index; the comparison logic compares the tag with each tag in the selected two sets and indicates a hit if a match; and otherwise allocates into one set of the two selected sets.