Abstract: A light-emitting device includes: a light-emitting element; a coating member that covers the light-emitting element; and two external connection electrodes exposed form a first surface of the coating member. Each of the external connection electrodes includes an electrode buried in the coating member; and a metal layer formed on the electrode. A surface of each of the metal layers is exposed from the first surface of the coating member. The first surface of the coating member includes a plurality of grooves between the external connection electrodes.

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes source select lines, word lines, drain select lines, and a bit line stacked on a substrate in which a first cell string region and a second cell string region are defined; channel layers and memory layers vertically passing through the source select lines, the word lines, and the drain select lines in each of the first cell string region and the second cell string region; and a common source line vertically passing through the source select lines, the word lines, and the drain select lines at centers of the first cell string region and the second cell string region, and extended to a lower side of the source select lines.

Abstract: A light emitting device, according to one embodiment, may comprise: a substrate; a first conductive semiconductor layer disposed on the substrate; an active layer disposed on the first conductive semiconductor layer and generating an ultraviolet light; a second conductive semiconductor layer disposed on the active layer; and a hole injection layer disposed between the active layer and the second conductive semiconductor layer and comprising a first layer comprising AlxGa1-xN (0<x?1) and a second layer comprising GaN. The embodiment has the hole injection layer to be multi-layered, thereby having the effect of effectively preventing the absorption of ultraviolet light.

Abstract: An optical device may include a sacrificial limiter filter including at least one layer of graphene disposed on a substrate. The at least one layer of graphene may be configured to absorb and scatter at least a portion of electromagnetic radiation incident on the at least one layer of graphene.

Abstract: A system and method for forming a sensor device with a buried first electrode includes providing a first silicon portion with an electrode layer and a second silicon portion with a device layer. The first silicon portion and the second silicon portion are adjoined along a common oxide layer formed on the electrode layer of the first silicon portion and the device layer of the second silicon portion. The resulting multi-silicon stack includes a buried lower electrode that is further defined by a buried oxide layer, a highly-doped ion implanted region, or a combination thereof. The multi-silicon stack has a plurality of silicon layers and silicon dioxide layers with electrically isolated regions in each layer allowing for both the lower electrode and an upper electrode. The multi-silicon stack further includes a spacer that enables the lower electrode to be accessible from a topside of the sensor device.

Abstract: The present disclosure relates to a TFT includes an active layer formed on a substrate, wherein the active layer includes a first semiconductor layer and a second semiconductor layer stacked together. The first semiconductor layer is made by Indium gallium zinc oxide (IGZO) having an atomic ratio In/(Ga+Zn) smaller than 50%, and the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) greater than 55%. The present disclosure also includes an array substrate having the TFT and the manufacturing method thereof. The array substrate may be adopted in LCD or OLED. The TFT adopts two layers of IGZO semiconductor materials to be the semiconductor of the active layer. Not only the demand toward the TFT characteristics may be satisfied, but also the carrier mobility rate of the IGZO active layer may be enhanced.

Abstract: A method for forecasting reduction in sunlight intensity due to cloud cover at a photovoltaic power plant is described. The method comprises determining characteristics of one or more clouds from sensors surrounding the photovoltaic power plant. The cloud characteristics are used to create a 3D map of the clouds. The 3D map in combination with information on the angle of the sun is used to create a 3D projection on the surface of the earth, resulting in a 2D surface irradiance map. The 2D surface irradiance map may be taken in successive projections or used in combination with wind speed data to forecast fluctuation in irradiance at the photovoltaic power plant. The forecasted reductions in power may be used to enact measures at the plant such as reducing the power output of inverters to prevent sudden fluctuations in the power output of the photovoltaic plant feeding the utility.

Abstract: A flat display panel and manufacturing method are disclosed. The flat display panel includes a first substrate, a second substrate disposed oppositely to the first substrate. The second substrate is provided with a material layer having multiple concave slots. Multiple spacers are disposed on the first substrate and facing toward the second substrate. Wherein, multiple spacers include multiple main spacers and auxiliary spacers. The multiple auxiliary spacers respectively face toward regions which the multiple concave slots are located on, and the multiple main spacers respectively face toward regions which the multiple concave slots are not located on. A height of each main spacer and a height of each auxiliary spacer are the same such that when the flat display panel is not pressed, supporting the flat display panel through the main spacers, and when the flat display panel is pressed, further supporting the flat display panel through the auxiliary spacers.

Abstract: A micro-electromechanical pressure transducer formed from a silicon die centers itself on a pedestal, formed from either a metal or a dielectric, by applying a predetermined amount of liquid epoxy adhesive to the square, top surface of the pedestal and allowing the liquid adhesive to distribute itself over the top surface. A MEMS die placed atop the liquid adhesive is centered on the top surface by surface tension between sides of the die and the top surface.

Abstract: A process for fabricating a LED lighting apparatus includes disposing a composite coating on a surface of a LED chip. The composite coating comprises a first composite layer having a manganese doped phosphor of formula I and a first binder, and a second composite layer comprising a second phosphor composition and a second binder. The first binder, the second binder or both include a poly(meth)acrylate. Ax[MFy]:Mn4+??(I) wherein A is Li, Na, K, Rb, Cs, or a combination thereof; M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Hf, Y, La, Nb, Ta, Bi, Gd, or a combination thereof; x is the absolute value of the charge of the [MFy] ion; y is 5, 6 or 7.

Abstract: An embodiment of a semiconductor device includes a transistor cell array having transistor cells in a semiconductor body. A planar gate structure is on the semiconductor body at a first side. Field electrode trenches extend into the semiconductor body from the first side. Each of the field electrode trenches includes a field electrode structure. A depth d of the field electrode trenches is greater than a maximum lateral dimension wmax of the field electrode trenches at the first side.

Abstract: A semiconductor structure comprising a first layer, a metal layer and a second layer is disclosed. The first layer comprises a recessed surface. The metal layer is above a portion of the recessed surface. The second layer is above the metal layer and confined by the recessed surface. The second layer comprises a top surface, a first lateral side and a second lateral side. The etch rate of an etchant with respect to the metal layer is greater than the etch rate of the etchant with respect to the second layer. The thickness of the second layer in the middle of the second layer is less than the thickness of the second layer at the first lateral side or the second lateral side. A method of forming a semiconductor structure is disclosed.

Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.

Abstract: A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity.

Abstract: An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

Abstract: An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.

Abstract: An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer.

Abstract: A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

Abstract: A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.

Abstract: Disclosed is an organic light emitting display device having excellent lifespan and current efficiency characteristics, as well as high luminance to provide increased resolution and improved reliability, and a method for manufacturing the same. The organic light emitting display device comprises a substrate having first, second, and third pixel regions; a first electrode arranged on the substrate; a second electrode arranged on the first electrode; and an organic layer arranged between the first electrode and the second electrode. The organic layer includes first, second and third organic layers on the first, second and third pixel regions, respectively. Each of the first, second and third organic layers includes a plurality unit organic layers and at least one charge generating layer arranged between the plurality of unit organic layers.