Abstract: A three-dimensional semiconductor memory device includes a stack structure disposed on a substrate and including lower and upper stack structures, first and second isolation trenches defining the stack structure, extending in a first direction, and spaced apart from each other in a second direction, a middle isolation trench penetrating the upper stack structure between the first and second isolation trenches and extending in the first direction, and a horizontal isolation pattern connected to the middle isolation trench and dividing the upper stack structure in the second direction. The horizontal isolation pattern includes horizontal isolation portions, each of which extends in the first direction and is offset from an extension line of the middle isolation trench in the second direction or an opposite direction to the second direction.

Abstract: The present disclosure provides a bonding method for a semiconductor substrate, which may improve flatness of a bonded substrate. The present disclosure further provides a bonded semiconductor substrate. The semiconductor substrate is thermally treated prior to bonding, and oxygen precipitates in the semiconductor substrate are partially or totally converted to interstitial oxygen atoms in the thermal treatment.

Abstract: A method to make light-emitting diode (LED) units include arranging LEDs in a pattern, forming an optically transparent spacer layer over the LEDs, forming an optically reflective layer over the LEDs, and singulating the LEDs into LED units. The method may further include, after forming the optically transparent spacer layer and before singulating the LEDs, forming a secondary light-emitting layer that conforms to the LEDs, cutting the LEDs to form LED groups having a same arrangement, spacing the LED groups on a support, and forming the optically reflective layer in spaces between the LED groups.

Abstract: A display device includes: a substrate including: first to third subpixels, an insulating layer including a trench on the substrate between at least two among the first to third subpixels, a first electrode on the insulating layer in each of the first to third subpixels, a fence in each of the first to third subpixels, the fence surrounding an edge of the first electrode, a light-emitting layer on the first electrode, the fence, and the insulating layer, a second electrode on the light-emitting layer, and a color filter layer including: a first color filter in the first subpixel, a second color filter in the second subpixel, and a third color filter in the third subpixel, wherein the second color filter is wider than the first color filter, and wherein the second color filter partially overlaps the first subpixel.

Abstract: An OLED including a substrate; a circuit region; reflective metal layers on the circuit region and including first to third reflective metal layers spaced apart from each other; an insulating layer including first to third insulating regions covering upper surfaces of the reflective metal layers and having a first to third thicknesses that are different from one another; first to third via plugs penetrating through the insulating layer to contact the reflective metal layers, first electrodes in contact with the via plugs, and covering a portion of an upper surface of the insulating layer; an organic light emitting layer on the first electrodes; and a second electrode on the organic light emitting layer, wherein the first to third via plugs include tungsten.

Abstract: A semiconductor device includes a semiconductor chip in which a field effect transistor mainly containing GaN is formed on a surface of a SiC semiconductor substrate. The semiconductor device includes a metal base on which a back surface of the semiconductor chip is mounted through a conductive adhesive material containing Ag and a resin mold configured to seal the semiconductor chip. A metal having wettability lower than wettability of Au or Cu with respect to Ag is exposed in a region extending along an edge of the back surface.

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A semiconductor device includes a conductive feature over a substrate, a ruthenium-containing feature disposed over the conductive feature, and a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature. The semiconductor device also includes a second barrier layer disposed over sidewalls of the first barrier layer, and a third barrier layer disposed over sidewalls of the second barrier layer. The first, second, and third barrier layers include different material compositions.

Abstract: An LED package structure and a carrier thereof are provided. The LED package structure includes a carrier, a plurality of LED chips, and an encapsulating colloid. The carrier includes a substrate, a ring-shaped first wall disposed on the substrate, and a ring-shaped second wall stacked on the first wall. A portion of the substrate surrounded by the first wall is defined as a die-bonding region, and the first wall, the second wall, and the die-bonding region jointly define an accommodating space. The LED chips are mounted on the die-bonding region and are arranged in the accommodating space. The encapsulating colloid is filled within the accommodating space, and the LED chips are embedded in the encapsulating colloid.

Abstract: A light-emitting element includes a first semiconductor layer, a second semiconductor layer, a light-emitting layer, a first electrode, and a second electrode. The first semiconductor layer includes gallium and nitrogen and is of an n-type. The second semiconductor layer includes gallium and nitrogen and is of a p-type. The light-emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer. The first semiconductor layer includes a first partial region and a first side surface region. The first partial region includes a first surface contacting the first electrode. The first side surface region includes a first side surface crossing a plane perpendicular to a first direction. The first direction is from the second semiconductor layer toward the first semiconductor layer.

Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.

Abstract: An apparatus and method for a detector are disclosed. The apparatus disclosed contains a non-absorbing layer shaped as one or more pyramids, one or more collector regions, an absorber layer disposed between the one or more collector regions and the non-absorbing layer, a first electrical contact, and a second electrical contact, wherein the absorber layer is configured to absorb photons of incident light and generate minority electrical carriers and majority electrical carriers, wherein the one or more collector regions are electrically connected with the absorber layer and with the first electrical contact for extracting the minority electrical carriers, and the absorber layer is electrically connected with the one or more collector regions and with the second electrical contact to extract the majority electrical carriers.

Abstract: The present invention seeks to provide cadmium-free quantum dots with a narrow fluorescence FWHM. The quantum dot does not contain cadmium and its fluorescence FWHM is 30 nm or less. The quantum dot is preferably a nanocrystal containing zinc and tellurium or zinc and tellurium and sulfur or zinc and tellurium and selenium and sulfur. Further, the quantum dot preferably has a core-shell structure in which the nanocrystal serves as a core and the surface of the core is coated with a shell.

Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.

Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Abstract: The light-emitting device includes a display unit in which rectangular light-emitting pixels are arranged, and a light-shielding portion that defines a light-emitting region in the display unit and shields light in a region other than the light-emitting region of the display unit, and at least a part of a boundary between the light-emitting region and the light-shielding portion has a curved shape.

Abstract: Display structures for controlling viewing angle color shift are described. In various embodiments, polarization sensitive diffusers, independent controlled cathode thicknesses, filtermasks, touch detection layers, and color filters are described.

Abstract: Provided is a semiconductor device. The device comprises an epitaxial layer that constitutes a part of an active cell region and is doped with impurities of a first conductivity type at a first concentration; a field stop region that is located below the epitaxial layer and doped with impurities of a second conductivity type at a second concentration which are then activated; and a collector region that is located below the field stop region 70 and is doped with impurities of a second conductivity type. The field stop region is formed by repeatedly alternately arranging regions in which the activation of the impurities of the first conductivity type is relatively strong and regions in which the activation of the impurities of the first conductivity type is relatively weak.