Abstract: The disclosure relates to an LED display module, and more particularly to an LED display module, in which a conductive metal thin film layer formed by deposition is used to configure lateral side wiring for connecting an upper circuit pattern and a lower circuit pattern of a substrate, thereby removing a bezel, and guaranteeing display quality because a division line or a bezel line is not seen even when a plurality of modules undergoes tiling to get a desired display size.

Abstract: An electrode and an organic electroluminescent device using the same are provided. The electrode comprises a first conductive layer (1), a second conductive layer (2) and a third conductive layer (3) that are arranged in a stacked manner The second conductive layer (2) has a single-layer structure or multi-layer composite structure formed by at least one of alkali earth metal, alkali earth metal alloy and alkali earth metal compound, and the third layer (3) has a work function of less than 3 eV. The respective conductive layers of the electrode can compensate with respect to the defects in one another, thereby making the performance of the electrode more stable. In the meantime, because the work function of the third conductive layer (3) is less than 3 eV, the barrier of organics-metal interface can be effectively reduced for guiding the electron injection, thereby increasing the light-emitting efficiency of device.

Abstract: Some embodiments include an integrated structure having a conductive region which contains one or more elements from Group 2 of the periodic table. Some embodiments include an integrated structure which has a conductive region over and directly against a base material. The conductive region includes one or more elements from Group 2 of the periodic table, and has a pair of opposing sidewalls along a cross-section. A capping material is over and directly against the conductive region. Protective material is along and directly against the sidewalls of the protective region.

Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

Abstract: A substrate processing technique includes: a first heating device configured to heat a substrate to a first processing temperature; a first process chamber provided with the first heating device; a second heating device configured to heat the substrate to a second processing temperature utilizing microwaves, the second processing temperature being higher than the first processing temperature; a second process chamber provided with the second heating device; a substrate placement portion configured to load and unload the substrate with respect to the first process chamber and the second process chamber by placing and rotating the substrate; and a controller configured to respectively control the first heating device, the second heating device, and the substrate placement portion.

Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.

Abstract: A Micro LED display panel, a method for fabricating the Micro LED display panel and a display device are provided. When the LED chip array is transferred, it may only be required to embed the LED chip array into the adhesive film layer. The LED chip array is bonded to the array substrate through the adhesive film layer. Then, unnecessary portions of the adhesive film layer and unnecessary LED chips are removed. It is not necessary to attach LED chips in the LED chip array one by one to the substrate by soldering, in which case the process of fabricating the Micro LED display panel is simplified, the difficulty in fabricating the Micro LED display panel is reduced, the influence of the high temperature generated by the soldering process on the LED chips is avoided, and damage to the LED chips during the transfer process is avoided.

Abstract: A display panel includes a base substrate, and thin film transistors positioned on the base substrate. Each thin film transistor includes a polysilicon layer. The display panel further includes a light-shielding layer for blocking ultraviolet (UV) light that is located at a side of the polysilicon layer away from the base substrate. An orthographic projection of the polysilicon layer on the substrate is in a range of an orthographic projection of the light-shielding layer on the substrate.

Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: A power MOSFET having a substrate that has a substrate surface into which a trench structure is introduced, wherein first trenches and second trenches form the trench structure. The first trenches and second trenches are arranged in alternation. The first trenches are filled at least partially with a first material and the second trenches are filled with a second material. The first material has a first conductivity type and the second material has a second conductivity type, the first conductivity type and the second conductivity type being different from each other.

Abstract: An optoelectronic component includes a carrier, and a housing material arranged above a top side of a carrier, wherein a cavity is configured in the housing material, a top side of a first optoelectronic semiconductor chip is arranged in the cavity, the first optoelectronic semiconductor chip has a first electrical connection pad arranged at the top side of the first optoelectronic semiconductor chip, and electrically conductively connects by a bond wire to a first contact pad arranged at the top side of the carrier, a first section of the bond wire is arranged in the cavity and a second section of the bond wire is embedded the housing material, a covering material is arranged in the cavity and covers at least one part of the top side of the first optoelectronic semiconductor chip, and the first section of the bond wire is embedded in the covering material.

Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The manufacturing method of the display substrate includes: forming a pattern of first transparent conductive layer, forming a passivation layer and forming a second transparent conductive layer on the passivation layer, forming a pattern of second transparent conductive layer, i.e., a slit electrode, the pattern of second transparent conductive layer including a plurality of sub-electrodes arranged at intervals and located in a display region of the display substrate; and removing a portion of the passivation layer which is in the display region and is not covered by the sub-electrodes, forming a pattern of passivation layer. The second transparent conductive layer is polycrystalline ITO.

Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.

Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: A trench MOS-type Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer opposite to the second semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench MOS gate that is embedded in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode.

Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.