Abstract: A method includes depositing a hardmask layer over a magnetoresistive (MR) structural layer formed on a substrate, the hardmask layer being formed from tungsten or a tungsten-based composition. A photoresist layer is deposited over the hardmask layer and is patterned to expose a first portion of the hardmask layer. A first etch process is performed to remove the first portion of the hardmask layer and expose a second portion of the MR structural layer and a dry etch process is performed to remove the second portion of the MR structural layer and produce an MR sensor structure. Following the dry etch process, a composite structure remains that includes the MR sensor structure and a hardmask section of the hardmask layer, the hardmask section overlying the MR sensor structure. A spacer formed from a protective, dielectric material layer may additionally be formed surrounding the composite structure.

Abstract: A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

Abstract: A method for manufacturing an interconnect structure with air gaps includes the following steps. A substrate including a first insulating layer formed thereon is provided. Plural conductive lines are formed in the first insulating layer. A patterned hard mask is formed on the first insulating layer and the conductive lines and exposes portions of the first insulating layer and portions of the conductive lines. The exposed portions of the first insulating layer are then removed to form a plurality of recesses in the first insulating layer. After that, a second insulating layer and a third insulating layer are formed in the recesses to seal the recesses and to form a plurality of air gaps in the recesses. At least two air gaps are respectively formed at two sides of one conductive line of the plurality of conductive lines. A via structure is then formed on the one conductive line.

Abstract: A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die disposed on the base substrate, the die including a semiconductor device, a solder bump disposed on a surface of the die, and configured to discharge heat generated in the die to an outside; and a solder ball disposed on another surface, opposite to the surface, of the die, and configured to transmit a signal, which is produced by the semiconductor device of the die, to an external device.

Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.

Abstract: The present disclosure provides a semiconductor structure, including a bottom terminal, a first middle terminal over the bottom terminal and separated from the bottom terminal by a high-k dielectric layer, a second middle terminal over the first middle terminal and separated from the first middle terminal by the high-k dielectric layer, a top terminal over the second middle terminal and separated from the second middle terminal by the high-k dielectric layer, a first via penetrating the bottom terminal and the second middle terminal, a second via penetrating the first middle terminal, a first passivation layer below the bottom terminal, and a second passivation layer over the top terminal.

Abstract: The magnetoresistance effect element includes a semiconductor layer, a first ferromagnetic layer and a second ferromagnetic layer. The semiconductor layer has a first region, a second region, and a third region. The first ferromagnetic layer is provided on the first region, the second ferromagnetic layer is provided on the second region, and the third region is sandwiched between the first region and the second region in the first direction. The third region has n-type conductivity, and crystal orientations of the semiconductor material in the first direction are substantially the same in the first region, the second region, and the third region. An interatomic distance of the third region in an upper surface neighboring region including the upper surface is larger than an interatomic distance of the first region in the upper surface neighboring region.

Abstract: A method of forming a segmented channel transistor device is provided. The method includes forming a stack of alternating sacrificial spacer segments and channel segments on a substrate. The method further includes forming an outer spacer liner on the sacrificial spacer segments and channel segments, and removing a portion of the outer spacer liner, sacrificial spacer segments, and channel segments to form stacked nanowire segments separated by remaining sacrificial portions. The method further includes removing the remaining sacrificial portions, and forming an inner spacer liner on the nanowire segments. The method further includes recessing the outer spacer liner and the inner spacer liner to form nanowire supports between the nanowire segments.

Abstract: A light emitting display device includes a substrate that includes a first pixel, a second pixel, a third pixel, and an infrared ray emission portion, the first pixel, the second pixel, and the third pixel representing different colors, a first electrode on the substrate, a second electrode that overlaps the first electrode, an emission layer between the first electrode and the second electrode, and an auxiliary layer between the first electrode and the emission layer. The emission layer may include a first emission layer in the first pixel and an infrared ray emission layer in the infrared ray emission portion, the auxiliary layer may include a first auxiliary layer in the first pixel, and the infrared ray emission layer and the first auxiliary layer may include the same material.

Abstract: Image sensors are provided. An image sensor includes a semiconductor substrate including a pixel region and an optical black region. The image sensor includes a plurality of photoelectric conversion regions in the pixel region. The image sensor includes a wiring structure on a first surface of the semiconductor substrate. The image sensor includes a light shielding layer on a second surface of the semiconductor substrate in the optical black region. Moreover, the image sensor includes a light shielding wall structure that is in the semiconductor substrate between the pixel region and the optical black region and that is connected to the light shielding layer.

Abstract: The invention relates to a chip card manufacturing method. According to this method, there are produced on the one hand, a module including a substrate supporting contacts on one face, and bonding pads on the other, on the other hand, an antenna on a support. The ends of the antenna are linked to lands of connection lands receiving a drop of soldering material on a connection portion. In order to make the soldered electrical connection between the module and the antenna reliable, the bonding pads extend over a zone covering a surface area less than that of the connection portions. The invention relates also to a chip card whose module includes bonding pads extending over a zone covering a surface area less than that of the connection portions.

Abstract: The present invention provides an integrated enhancement/depletion mode HEMT and a method for manufacturing the same, by which method an enhancement mode transistor and a depletion mode transistor can be integrated together, which is beneficial for increasing the application of gallium nitride HEMT devices and improving the characteristics of circuits, and lay a foundation for realizing monolithic integration of high-speed digital/analog mixed signal radio frequency circuits. At the same time, by using a regrowth technology of a barrier layer, electrons generated by impurities are made part of a conductive channel, thus the concentration of the two-dimensional electron gas is increased, and the conductive performance is improved while preventing excessive electrons from interfering with the devices.

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

Abstract: A photosensitive transistor device, on a semiconductor on insulator substrate, the photosensitive zone being formed in a substrate support layer and being arranged so that the concentration of photogenerated charges in the photosensitive zone can be increased towards a given zone facing the channel zone of the transistor.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in ring shape enclosed a vertical P-N junction. For each deep trench, a corresponding wider ring-shape P+ region is created on top of a N? epi layer. This enclosed deep trench surrounding a vertical P-N junction and a thinner N? epitaxial layer allow higher reverse bias voltage and low leakage current. In another embodiment, an enclosed deep trench in ring shape surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. The structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

Abstract: A method for fabricating a semiconductor structure includes providing a base substrate, including a substrate, a plurality of gate structures formed on the substrate, and a cap layer formed on the plurality of gate structures; removing the cap layer to form a trench on each gate structure; and forming a substitution layer in the trench. The dielectric constant of the substitution layer is smaller than the dielectric constant of the cap layer.

Abstract: An integrated circuit having an epitaxial source and drain, which reduces gate burnout and increases switching speed so that is suitable for high voltage applications, is provided. The integrated circuit includes a semiconductor substrate having a high voltage N-well (HVNW) and a high voltage P-well (HVPW). The integrated circuit further includes a high-voltage device on the semiconductor substrate. The high-voltage device includes an epitaxial p-type source disposed in the HVNW, an epitaxial p-type drain disposed in the HVPW, and a gate arranged between the epitaxial p-type source and the epitaxial p-type drain on a surface of the semiconductor substrate.

Abstract: The present invention relates to a method for the deposition of at least one layer of an organic material on a substrate by (a) providing a source of a solid organic material in an atmosphere at a pressure comprised between 50 and 200 kPa, (b) heating said organic material to a first temperature to produce a vapor of said organic material, (c) exposing at least one surface of a substrate having a second temperature lower than said first temperature to said vapor to deposit organic material from said vapor onto said at least one surface of said substrate.

Abstract: An image sensor including at least one pixel for collecting charge in its photodiode is provided. The image sensor comprises: a substrate having a first surface on a front side and a second surface on a back side, a photodetector formed in the silicon substrate and having a light-receiving surface on the second surface, and a first layer with positive charges disposed on the second surface, the first layer being configured to form an electron accumulation region at the light-receiving surface of the photodetector for suppressing a dark current at a back side interface of the image sensor. A method for fabricating an image sensor including a first layer with positive charges is also provided.

Abstract: A sensor assembly for being mounted on a circuit board comprises an interposer with at least one opening extending between a first and a second main surface of the interposer. The interposer comprises at least two stress decoupling elements, each comprising a flexible structure formed by a respective portion of the interposer being partially enclosed by one of the at least one opening. A sensor die is connected to the flexible structures on the first main surface. At least two board connection elements are arranged on the first main surface and adapted for connecting the assembly to the circuit board.