Patents Examined by Sue Tang
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Patent number: 11276646Abstract: An electronic component module includes a first substrate mounted on an upper surface of a second substrate such that at least a portion of a lower surface of the first substrate is exposed externally of the second substrate and electronic devices mounted on the first substrate and the second substrate, including at least one electronic device mounted on the upper surface of the second substrate.Type: GrantFiled: May 28, 2019Date of Patent: March 15, 2022Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jong Yun Kim, Chang Ju Lee, Gye Won Lee, Hee Sun Oh, Hong Seok Lee
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Patent number: 11239155Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.Type: GrantFiled: December 22, 2019Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
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Patent number: 11239241Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.Type: GrantFiled: September 26, 2019Date of Patent: February 1, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pin-Hong Chen, Yi-Wei Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Tsun-Min Cheng, Chi-Mao Hsu
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Patent number: 11227918Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: GrantFiled: May 24, 2019Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Patent number: 11227913Abstract: A second source portion having an impurity concentration lower than that of a first source portion, both forming a source region, includes a first sub-portion having a depth from a bottom surface of the first source portion down to a second height higher than a first height, and a second sub-portion having an upper surface in contact with a part of a bottom surface of the first sub-portion, one side surface in a second direction perpendicular to a first direction in contact with an outer side surface of the trench, another side surface in the second direction, both side surfaces in the first direction, and a bottom surface in contact with the base layer, and having a depth from a bottom surface of the first sub-portion up to at least the first height.Type: GrantFiled: July 17, 2020Date of Patent: January 18, 2022Assignee: ABLIC INC.Inventors: Yuki Osuga, Hirofumi Harada
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Patent number: 11227887Abstract: A semiconductor device structure for sensing an incident light includes a substrate, a passivation layer and a wiring structure. The substrate has a device embedded therein. The passivation layer is disposed on the substrate, where the passivation layer has a first side and a second side opposite to the first side, the first side of the passivation layer includes microstructures disposed on the substrate, and the second side of the passivation layer is a continuous flat plane, wherein each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed on the substrate, where the writing structure includes at least one contact and metal interconnection patterns respectively formed in different dielectric layers, and the at least one contact and the metal interconnection patterns are electrically connected, where the substrate is located between the passivation layer and the wiring structure.Type: GrantFiled: October 8, 2019Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Ping Pan, Hung-Jen Hsu
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Patent number: 11217549Abstract: A driving chip and a display device are provided herein. The driving chip includes a substrate, a plurality of connection bumps and a plurality of buffer bumps on the substrate. Each of the connection bumps and the buffer bumps is disposed on a first substrate of the substrate. The buffer bump includes a first end face with a height a, and the connection bump has a connection bump end face with a height b, a<b. The height is a distance from a corresponding end face of the connection bump or the buffer bump to the first surface. With the buffer bumps on the driving chip, stress buffering can be achieved, which can further improve the bonding effect of the driving chip.Type: GrantFiled: October 30, 2018Date of Patent: January 4, 2022Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Lianbin Liu, Hengzhen Liang, Chuanyan Lan, Guoqiang Wu
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Patent number: 11217596Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.Type: GrantFiled: March 20, 2019Date of Patent: January 4, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu
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Patent number: 11217658Abstract: The disclosure relates to a semiconductor device, including a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, the second conductivity type being different than the first conductivity type. The semiconductor device also includes an isolation structure electrically isolating a first region of the semiconductor layer from a second region of the semiconductor layer. A shallow trench isolation structure vertically extends from a surface of the semiconductor layer into the first region of the semiconductor layer. An electrical resistor is formed on the shallow trench isolation structure.Type: GrantFiled: May 28, 2019Date of Patent: January 4, 2022Assignee: Infineon Technologies AGInventors: Andreas Meiser, Grzegorz Kozlowski, Till Schloesser
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Patent number: 11211503Abstract: In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.Type: GrantFiled: July 26, 2019Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 11211333Abstract: The present disclosure describes a semiconductor structure includes a first chip with a first conductive line and a first conductive island formed on the first conductive line. The first chip also includes a first plurality of vias formed in the first conductive island and electrically coupled to the first conductive line. The semiconductor structure further includes a second chip bonded to the first chip, where the second chip includes a second conductive line and a second conductive island formed on the second conductive line. The second chip also includes a second plurality of vias formed in the second conductive island and electrically coupled to the second conductive line.Type: GrantFiled: July 10, 2019Date of Patent: December 28, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Po-Hsiang Huang, Noor Mohamed Ettuveettil
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Patent number: 11211548Abstract: This spin current magnetization reversal element includes a magnetoresistance effect element having a first ferromagnetic metal layer having a fixed magnetization direction, a second ferromagnetic metal layer having a variable magnetization direction, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a first direction that intersects the stacking direction of the magnetoresistance effect element, and contacts the surface of the magnetoresistance elect element on the side facing the second ferromagnetic metal layer, wherein at least one surface of the second ferromagnetic metal layer in the stacking direction has an inclined surface that is inclined in the first direction, and the direction of magnetization of the second ferromagnetic metal layer is inclined due to the inclined surface.Type: GrantFiled: July 19, 2019Date of Patent: December 28, 2021Assignee: TDK CORPORATIONInventors: Tomoyuki Sasaki, Tatsuo Shibata, Tohru Oikawa
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Patent number: 11205588Abstract: Interconnect structures having enhanced reliability is provided in which an electrically conductive structure having a line portion and a via portion is formed utilizing a subtractive process. In some embodiments, a non-conductive barrier liner is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls and a topmost surface of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure. In other embodiments, a conductive barrier spacer is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure.Type: GrantFiled: July 10, 2019Date of Patent: December 21, 2021Assignee: International Business Machines CorporationInventors: Baozhen Li, Chih-Chao Yang, Naftali E. Lustig
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Patent number: 11205598Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.Type: GrantFiled: September 24, 2019Date of Patent: December 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jam-Wem Lee
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Patent number: 11205622Abstract: To overcome the problem of devices in a multi-chip package (MCP) interfering with one another, such as through electromagnetic interference (EMI) and/or radio-frequency interference (RFI), the chip package can include an electrically conductive stiffener that at least partially electrically shields the devices from one another. At least some of the devices can be positioned in respective recesses in the stiffener. In some examples, when the devices are positioned in the recesses, at least one device does not extend beyond a plane defined by a first side of the stiffener. Such shielding can help reduce interference between the devices. Because device-to-device electrical interference can be reduced, devices on the package can be positioned closer to one another, thereby reducing a size of the package. The devices can electrically connect to a substrate via electrical connections that extend through the stiffener.Type: GrantFiled: May 28, 2019Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong
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Patent number: 11195800Abstract: An electronic device module includes a substrate, a first device and a second device mounted on the substrate, and a shielding frame mounted on the substrate to accommodate the first device. The shielding frame includes a heat dissipating portion stacked on the first device, and posts extended from an edge of the heat dissipating portion and spaced apart from each other. A spacing distance between the posts is smaller than a wavelength of an electromagnetic wave introduced into the first device or output from the first device.Type: GrantFiled: May 28, 2019Date of Patent: December 7, 2021Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Jung Mok Jang
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Patent number: 11195994Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.Type: GrantFiled: November 20, 2019Date of Patent: December 7, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Chen-Yi Weng, Si-Han Tsai, Jing-Yin Jhang, Yu-Ping Wang
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Patent number: 11189659Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.Type: GrantFiled: May 28, 2019Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Jiunyu Tsai, Sheng-Huang Huang
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Patent number: 11177228Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.Type: GrantFiled: June 10, 2019Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
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Patent number: 11171147Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.Type: GrantFiled: March 20, 2019Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu