Abstract: A memory system that controls latency for a plurality of clock signals and outputs at least one of read data and write data includes a memory controller configured to receive a data output command from a host, generate a plurality of clock signals for outputting data, and control latency of the plurality of clock signals, and an input/output (I/O) circuit configured to output data based on the clock signals having the controlled latency.

Abstract: A memory system includes a plurality of memories, each including a plurality of data input terminals; and a memory controller configured to continuously transfer a first codeword and a second codeword to the data input terminals of the memories during a write operation.

Abstract: A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.

Abstract: Memory clock drivers, memories, and methods of operating memory clock drivers are provided. A memory device contains two memory clock drivers disposed opposite each other across an array of rows of memory cells. The memory clock drivers contain decoders, which decode an address corresponding to one or more rows of memory cells. The decoders are configured to decode the address to provide a plurality of word line signals to the corresponding rows of memory cells. The memory device also includes a row select circuit, which receives a row select address and activates a corresponding row of memory cells. The memory device includes control circuitry to control the arrays of memory cells at a local and a global level, as well as I/O modules to send signals to different parts of the memory device and integrate the memory device into external devices.

Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes a master chip and a plurality of slave chips. The master chip and the slave chips are each provided with a first transmission terminal and a second transmission terminal, where the first transmission terminals are connected to each other, and the second transmission terminals are connected to each other; and a first signal receiver and an address transmitter are provided in the master chip, and a second signal receiver is provided in the slave chip, the address transmitter is configured to send an address signal; a current slave chip sends the ZQ flag signal after completing the calibration; and the address transmitter is configured to send a next address signal.

Abstract: A memory packaged chip and a signal processing method therefor are provided. The memory packaged chip includes at least a memory chip and an expander chip capable of receiving a same external input signal; there are a pair of inter-chip pins connected to each other between the memory chip and the expander chip; and the memory chip generates a first control signal according to the external input signal, and transmit the first control signal to the expander chip through the pair of inter-chip pins to disable or enable an input function of the expander chip.

Abstract: There is provided a semiconductor device, which includes a calibration code generator circuit configured to generate a calibration code according to changes in external conditions, a first driver circuit configured to output a data signal with an impedance value controlled by the calibration code, an emphasis control circuit configured to generate an emphasis data signal using the data signal, and to change the calibration code according to an operating frequency to generate an emphasis code; and a second driver circuit configured to output the emphasis data signal with an impedance value controlled by the emphasis code.

Abstract: A memory device includes a memory cell array including a plurality of rows, an ECC engine configured to determine a health level for each of the plurality of rows based on the number of corrections of errors of data read from each of the plurality of rows, a control logic configured to determine a victim row address based on the health level and the number of accesses for each of the plurality of rows, and a refresh control circuit configured to perform a refresh on a row corresponding to the determined victim row address.

Abstract: One example includes an integrated circuit with a sense amplifier that includes a first inverter having a first positive power terminal, a first input and a first output; and a second inverter having a second positive power terminal, a second input connected to the first output and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power terminal. A fuse is connected between the positive voltage rail and the first positive power terminal.

Abstract: A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.

Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

Abstract: Embodiments of the present disclosure provide a word line driver, a word line driver array, and a semiconductor structure, relating to the technical field of semiconductors. The word line driver includes: a zeroth P-channel metal oxide semiconductor (PMOS) transistor, a zeroth N-channel metal oxide semiconductor (NMOS) transistor, and a first NMOS transistor, the zeroth PMOS transistor being provided with a gate connected to a gate of the first NMOS transistor and configured to receive a first control signal, a source configured to receive a second control signal, and a drain connected to a drain of the first NMOS transistor, the zeroth NMOS transistor being provided with a gate configured to receive a second control complementary signal, and a drain of the zeroth NMOS transistor and the drain of the first NMOS transistor being configured to be connected to a word line.

Abstract: A semiconductor memory device includes: a memory cell region including normal cells and row-hammer cells coupled to each of a plurality of rows, wherein the row-hammer cells of a selected row are suitable for storing first data and second data, the first data representing a number of accesses to the selected row and the second data denoting whether to refresh second adjacent rows of the selected row; and a refresh control circuit suitable for: selecting a sampling address based on the first data read from a row corresponding to an input address when an active command is inputted, determining, in response to a refresh command, whether to refresh first adjacent rows of a target row corresponding to the sampling address, and determining, in response to the refresh command, whether to refresh second adjacent rows of the target row based on the second data read from the target row.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell string including a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform an operation that applies an operating voltage to a selected word line and applying a pass voltage to unselected word lines, among the plurality of word lines, and an operation controller configured to control the peripheral circuit to perform, after the operation has been performed, a discharge operation that sequentially decreases voltages of the plurality of word lines that range from at least one central word line located in a central portion in relation to the memory cell string to a word line, among the plurality of word lines, located in an outermost portion in relation to the memory cell string, adjacent to a select line.

Abstract: In some embodiments, a programmable circuit configured to store a shift setting for a mode register parameter, and a shift circuit is configured to receive a first value of a mode register parameter. In response to the shift setting signal having a first value, the shift circuit is configured to adjust the first value of the mode register parameter to provide the mode register parameter having a second value. In response to the shift setting signal having a second value, the shift circuit is further configured to provide the first value of the mode register parameter as the second value of the mode register parameter. Circuitry coupled to an input/output terminal is configured to set a configuration based on the second value of the mode register parameter. The mode register parameter includes an on-die termination (ODT) parameter and the circuitry includes an ODT circuit, in some examples.

Abstract: A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

Abstract: A voltage generation circuit and a semiconductor memory device capable of decreasing the layout size and the consumed current are provided. A voltage generation circuit includes a plurality of voltage generation units which generate different output voltages based on an external power supply voltage. Each of the plurality of voltage generation unit comprises a plurality of resistors that are connected in series to detect the output voltages. At least one of these resistors is coupled to and shared by the plurality of voltage generation units.

Abstract: Disclosed is a memory device including a magnetic memory element. The memory device includes a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, a voltage generator configured to generate a code value based on the value of the write voltage, and a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region.

Abstract: A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least