Abstract: Embodiment relates to a data transmission circuit. In the circuit, an encoding circuit is configured to generate check code data according to first data on a first data line; a comparison circuit is configured to compare the first data with second data on a second data line to output a comparison result indicating whether number of different bits between the first data and the second data exceeds a preset threshold; a buffer circuit is configured to transmit the first data or opposite data of the first data to the second data line according to the comparison result; the buffer circuit is also configured to transmit the check code data to the second data line; a first read-write conversion subcircuit is configured to transmit the first data or the opposite data of the first data transmitted to the second data line to a third data line according to the comparison result.

Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.

Abstract: A memory access controller includes a request issuing circuit to issue a user request in response to a memory request, issue a refresh request at first issuing intervals, and issue a scrubbing request at second issuing intervals; and a command issuing circuit to issue a first active to a memory via a row command bus and issue M reads to the memory via a column command bus after the first active is issued, when memory access for the user request is to be executed, issue refresh to the memory via the row command bus when the memory access for the refresh request is executed, and issue a second active to the memory via the row command bus and issues N (>M) reads to the memory via the column command bus after the second active is issued, when the memory access for the scrubbing request is to be executed.

Abstract: A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and an equalizer. The data input circuit is configured to receive an input signal, and the latch circuit is connected to the data input circuit and configured to output an output signal in response to the input signal. The equalizer includes a first transistor having a source connected to latch circuit; and a second transistor having a source connected to the latch circuit and a gate connected to a gate of the first transistor.

Abstract: An accelerator circuit is provided that includes an inverter chain having an input coupled to a data line and a sense circuit having inputs coupled to an output of the inverter chain and the data line. The sense circuit is configured to sense a rise toward a supply voltage on the data line or a fall toward a ground voltage on the data line. The accelerator circuit further includes an amplify circuit having inputs coupled to outputs of the sense circuit and an output coupled to the data line, where the amplify circuit is configured to amplify the data line toward the supply voltage or toward the ground voltage based on amplify enable signals output by the sense circuit.

Abstract: A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.

Abstract: The application provides a content addressable memory (CAM) memory device, a CAM memory cell and a method for searching and comparing data thereof. The CAM memory device includes: a plurality of CAM memory cells; and an electrical characteristic detection circuit coupled to the CAM memory cells; wherein in data searching, a search data is compared with a storage data stored in the CAM memory cells, the CAM memory cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM memory cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.

Abstract: The present disclosure relates to an electronic device. A memory device according to the present disclosure includes a memory block coupled to a plurality of local word lines, a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines and configured to perform an operation on the memory block, and a control logic configured to control the peripheral circuit to cause or increase a leakage current of the pass switch circuit to discharge potential levels of the plurality of local word lines when the memory device enters a ready state after the operation.

Abstract: The present invention provides a memory controller including a plurality of channels. A first channel of the plurality of channels includes a first transmitter, a first pull-up variable resistor and a first pull-down variable resistor, wherein the first transmitter is configured to generate a first data signal to a memory module, the first pull-up variable resistor is coupled between a supply voltage and an output terminal of the first transmitter, and the first pull-down variable resistor is coupled to the output terminal of the first transmitter. The control circuit is coupled to the plurality of channels, and is configured to control the first pull-up variable resistor and/or the first pull-down variable resistor according to a reference voltage used by the memory module.

Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.

Abstract: In an example, an apparatus includes a memory array in a first region and decode circuitry in a second region separate from a semiconductor. The decode circuitry is coupled to an access line in the memory array.

Abstract: A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.

Abstract: A system includes a memory device having memory cells and a processing device operatively coupled to the memory device. The processing device is to perform operations including: determining a length of time the memory device has been powered off; and in response to determining that the length of time satisfies a threshold value: for each of multiple groups of memory cells, asserting a corresponding flag; determining, based on the length of time, one or more adjusted demarcation voltages to be used in reading a state of the multiple groups of memory cells; and storing the one or more adjusted demarcation voltages for use in performing memory operations.

Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block comprising a plurality of key tables each storing a respective plurality of stored search keys. The memory system further includes a processing device that receives, from a requestor, an input search key and an indication of one of the plurality of key tables and identifies a match between the input search key and one of the plurality of stored search keys in the one of the plurality of key tables. The one of the plurality of stored search keys has an associated offset value indicating a location in a sorted string table (SSTable) corresponding to the one of the plurality of key tables. The processing device further reads the offset value from the one of the plurality of key tables and returns, to the requestor, the offset value read from the one of the plurality of key tables. The requestor can retrieve, from the location in the SSTable, data representing a value associated with the input search key.

Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.

Abstract: Various embodiments include a memory device that is capable of performing write training operations, to determine that certain timing conditions are met, without storing data patterns in memory. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern being transmitted to the memory device by an external memory controller. If the data pattern generated by the memory device matches the data pattern received from the memory controller, then the memory device stores a pass status in a register. If the data patterns do not match, then the memory device stores a pass status in a register. The memory controller reads the register to determine whether the write training passed or failed.

Abstract: A memory system is provided to include a storage device including memory cells for storing data, and a controller in communication with an external device and configured to control the storage device based on a request from the external device. The controller is configured to receive a request from the external device to perform a refresh operation of re-writing stored data in the memory cells, read data from the memory cells included in the storage device, set a refresh period based on a number of fail bits included in the read data and a temperature of the controller or the storage device, and perform the refresh operation of the storage device based on the refresh period.

Abstract: Various embodiments include a memory device that is capable of performing command address interface training operations, to determine that certain timing conditions are met, with fewer I/O pins relative to prior approaches. Prior approaches for command address interface training involve loading data via a set of input pins, a clock signal, and a clock enable signal that identifies when the input pins should be sampled. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern continuously being transmitted to the memory device by an external memory controller. The memory device compares the generated data pattern with the received data pattern and transmits the result of the comparison on one or more data output pins. The memory controller receives and analyzes the result of the comparison to determine whether the command address interface training passed or failed.

Abstract: A memory system includes a memory device configured to monitor a first oscillator count value for a write data strobe signal for sampling a data signal at a first temperature and a second oscillator count value for the write data strobe signal for sampling the data signal at a second temperature, and a memory controller configured to determine a weight based on the first oscillator count value and the second oscillator count value, wherein the memory device is configured to sample the data signal by adjusting a delay on a transfer path of the write data strobe signal according to a change in temperature of the memory device based on the weight.