Patents Examined by Sultana Begum
  • Method for managing flash memory module and associated flash memory controller and electronic device based on timing of dummy read operations
    Patent number: 11487655
    Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 1, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
  • Semiconductor memory device to control operating timing based on temperature of the memory device
    Patent number: 11488652
    Abstract: A semiconductor memory device can appropriately control operation timing, based on changes in the environment (for example, power supply voltage and temperature, etc.) when in use. The semiconductor memory device includes a temperature sensor 18 that detects the temperature of the semiconductor memory device, a voltage detection portion (composed of a ring oscillator 14 and a counter 15) that detects the power supply voltage of the semiconductor memory device, and a control portion 10 that controls the operation timing in the semiconductor memory device to meet specific conditions, according to the temperature detected by the temperature sensor 18 after the power is applied and the voltage detected by the voltage detection portion after the power is applied.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: November 1, 2022
    Assignee: WINDBOND ELECTRONICS CORP.
    Inventor: Kaoru Mori
  • Systems and methods for improving power efficiency in refreshing memory banks
    Patent number: 11488651
    Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, Debra M. Bell, George B. Raad, Brian P. Callaway, Joshua E. Alzheimer
  • Nonvolatile memory device and method for operating with varying programming time
    Patent number: 11482288
    Abstract: A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: October 25, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seul Bee Lee, Dong Hun Kwak, Jong-Chul Park
  • Reset verification in a memory system by using a mode register
    Patent number: 11474698
    Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Memory architecture with pulsed-bias power
    Patent number: 11468941
    Abstract: Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: October 11, 2022
    Assignee: Arm Limited
    Inventors: Akash Bangalore Srinivasa, Andy Wangkun Chen, Penaka Phani Goberu, Yew Keong Chong
  • Techniques for initializing resistive memory devices by applying voltages with different polarities
    Patent number: 11468947
    Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 11, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventors: Zhichao Lu, Brent Haukness, Gary Bronner
  • Wordline capacitance balancing
    Patent number: 11462289
    Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Corrado Villa, Shane D. Moser
  • Methods of activating input/output lines of memory devices, and related devices and systems
    Patent number: 11462261
    Abstract: A method of operating a memory device is disclosed. A method may include generating a first control signal to activate a first number of main input/output (MIO) lines associated with a first data terminal region of a memory bank at a first time. The method may also include generating a second control signal to activate a second number of MIO lines associated with a second data terminal region of the memory bank at a second, subsequent time. Further, the method may include resetting each of the first control signal and the second control signal in response to a command.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yosuke Takano, Atsushi Shimizu
  • Control device and memory system for deep power-down mode
    Patent number: 11456026
    Abstract: A control device and a memory system are provided. The control device includes a first peripheral circuit group and a second peripheral circuit group. The first peripheral circuit group and a memory array are driven by a first voltage in a standby mode. The first peripheral circuit group provides a control command when recognizing that a command string is a deep power-down (DPD) execution command string. When receiving the control command, the second peripheral circuit group provides a DPD signal having a first logic value to stop providing the first voltage so that the memory system enters a DPD mode. In the DPD mode, when recognizing that the command string is a DPD exit command string, the second peripheral circuit group provides a DPD signal having a second logic value to provide the first voltage so that the memory system enters standby mode.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: September 27, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Liang-Hsiang Chiu, Yu-Chieh Chen
  • Flash memory device with programmable logic circuit
    Patent number: 11456047
    Abstract: Aspects of the disclosure provide a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled with the memory cell array. The memory cell array includes a plurality of memory cells. The peripheral circuitry includes programmable logic circuit that is configured, after the semiconductor memory device is powered on, to perform logic functions.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: September 27, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Huangpeng Zhang, Shiyang Yang, Yu Wang, Huamin Cao, Ting Li, Xu Hou
  • Relinking scheme in sub-block mode
    Patent number: 11456050
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow sub-blocks with different sub-block addresses to be linked across multiple planes to form metablocks. The memory includes multiple blocks in different planes, where each of the blocks includes multiple sub-blocks. The controller links a first sub-block in a first plane and a second sub-block in a second plane with different sub-block addresses to form the metablock. After forming the metablock, the controller programs different word lines in the first and second sub-blocks when writing data to the metablock. Thus, the controller may write data to linked or relinked metablocks with different sub-block addresses, thereby improving die yield and memory capacity of the storage device.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 27, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chandramani, Sagar Shirpimutt
  • Electronic devices performing temperature information update operation
    Patent number: 11423969
    Abstract: An electronic device includes a controller and a semiconductor device. The controller outputs a clock signal and a command signal having a first setting combination or a second setting combination and receives a temperature information signal. The semiconductor device compares an input time of a latch signal generated based on the command signal having the first setting combination with an input time of a temperature output control signal generated internally. In addition, the semiconductor device updates a temperature code according a comparison result of the input times of the temperature output control signal and the latch signal to generate the temperature information signal.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyun Seung Kim, Noh Hyup Kwak, Jin Suk Oh, Kyong Ha Lee
  • Max pooling processor based on 1T1R memory
    Patent number: 11416744
    Abstract: The present disclosure belongs to the technical field of artificial neural networks, and provides to a max pooling processor based on 1T1R memory, comprising an input module, a max pooling operation module, and an output module; the input module is configured to transmit an operating voltage according to the convolution result in the convolutional neural network; the 1T1R memory in the max pooling operation module is configured to adjust a conductance value of the RRAM according to the gate voltage of the transistor therein to achieve the max pooling operation by using the non-volatile multi-value conductance regulation characteristic of the RRAM, and store a max pooling result; and the output module is configured to read the max pooling result and output it.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 16, 2022
    Assignee: Huazhong University of Science and Technology
    Inventors: Yi Li, Rui Kuang, Xiang-Shui Miao
  • Method and apparatus in memory for input and output parameters optimization in a memory system during operation
    Patent number: 11416250
    Abstract: In some embodiments, a programmable circuit configured to store a shift setting for a mode register parameter, and a shift circuit is configured to receive a first value of a mode register parameter. In response to the shift setting signal having a first value, the shift circuit is configured to adjust the first value of the mode register parameter to provide the mode register parameter having a second value. In response to the shift setting signal having a second value, the shift circuit is further configured to provide the first value of the mode register parameter as the second value of the mode register parameter. Circuitry coupled to an input/output terminal is configured to set a configuration based on the second value of the mode register parameter. The mode register parameter includes an on-die termination (ODT) parameter and the circuitry includes an ODT circuit, in some examples.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Elancheren Durai
  • Microelectronic device testing, and related devices, systems, and methods
    Patent number: 11410742
    Abstract: Microelectronic device testing, and related methods, devices, and systems, are described herein. A device may include a memory array including a number of rows and a number of columns. The memory device may further include circuitry coupled to the memory array. The circuitry may be configured to perform a testing operation on each row of the number of rows to detect: a first fail of a first row of the number of rows; and a set of additional fails associated with a set of rows of the number of rows. The circuitry may also be configured to determine whether the set of rows is adjacent the first row. Further, in response to determining that the set of rows is adjacent the first row, the circuitry may be configured to generate a signal indicative of a failure of a column of the number of columns.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Yoshinori Fujiwara
  • I/O buffer offset mitigation while applying a same voltage level to two inputs of an input buffer
    Patent number: 11410730
    Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Ramin Ghodsi
  • Runtime identification of bad memory cells based on difference between data pattern and read data
    Patent number: 11404135
    Abstract: Technologies are provided for runtime identification of bad memory cells. An uncorrectable error can be detected in data stored in a plurality of memory cells of a memory device. Patterned data can be written to the plurality of memory cells that stored the data in which the uncorrectable error was detected. The data stored in the plurality of memory cells can be read and compared to the patterned data. One or more of the memory cells can be identified as bad memory cells based on differences between the patterned data and the data read from the plurality of memory cells. In at least some embodiments, the one or more identified bad memory cells can be omitted from subsequent data storage operations. Additionally or alternatively, the one or more identified bad memory cells can be repaired, for example, by using a post-package repair operation.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: August 2, 2022
    Assignee: Amazon Technologies, Inc.
    Inventor: Jonathan Parker
  • Memory cell programming applying a programming pulse having different voltage levels
    Patent number: 11404125
    Abstract: Methods of operating a memory, and memories configured to perform such methods, might include applying a programming pulse having a plurality of different voltage levels to a selected access line during a programming operation, and for each group of memory cells of a plurality of groups of memory cells of a plurality of memory cells selected for programming, enabling that group of memory cells for programming during a respective portion of the duration of the programming pulse of a corresponding voltage level of the plurality of different voltage levels, wherein memory cells of the plurality of memory cells selected for programming and having a particular intended data state are members of more than one of the groups of memory cells, and at least one of the groups of memory cells comprises a memory cell having the particular intended data state and a memory cell having a different intended data state.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Aaron S. Yip
  • Method and memory device with increased read and write margin
    Patent number: 11404140
    Abstract: A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell for a memory operation. The reference voltage generator is configured to generate a reference voltage based on at least one of a temperature of the memory array or a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hung-Chang Yu