Abstract: Disclosed are systems for wireless energy transfer including transcutaneous energy transfer. Embodiments are disclosed for user interface (UI) hubs to connect multiple batteries and to output system information to a patient. Embodiments are further disclosed for garments and devices to be worn by a patient requiring treatment. The garments are configured for a desired placement of a transmitter coil relative to a body of the patient and for facilitating patient comfort and quality of life. Methods for manufacturing and using the devices and the systems are also disclosed.

Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within said each power island. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of said one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of said one power island of the plurality of power islands to the target power level.

Abstract: Methods and apparatus relating to diagnostic testing of FPGAs for safety critical systems are described. In an embodiment, logic circuitry (e.g., a processor) performs one or more diagnostic operations on a portion of a Field Programmable Gate Array (FPGA) based on one or more test vectors. Memory stores the one or more test vectors. The logic circuitry performs the one or more diagnostic operations on the portion of the FPGA during runtime. Other embodiments are also disclosed and claimed.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for charging a multi-stack battery pack. For example, certain aspects provide a circuit for charging a battery pack having multiple battery cells. The circuit generally includes a voltage regulator circuit and charge pump circuitry having an input coupled to an output of the voltage regulator circuit, and an output coupled to a first battery charging terminal. In certain aspects, the first battery charging terminal may be configured to be coupled to a terminal of a first battery cell of the multiple battery of the battery pack.

Abstract: A circuit design tool places a circuit design, and after placing detects a hold violation of a path between a first flip-flop on a first IC die and a second flip-flop on a second IC die. The circuit design tool selects a window size based on an amount of the hold violation and determines an alternative path having a delay that resolves the hold violation. The alternative path is restricted to resources within an area of the window size on the second IC die. The circuit design tool replicates a plurality of instances of the alternative path in a plurality of areas of the second IC die and then routes the circuit design using the plurality of instances of the alternative path.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a capacitance difference between capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.

Abstract: A memory optimization method includes identifying, within a circuit design, a memory having an arithmetic operator at an output side and/or an input side of the memory. The memory may include a read-only memory (ROM). In some examples, an input of the arithmetic operator includes a constant value. In some embodiments, the memory optimization method further includes absorbing a function of the arithmetic operator into the memory. By way of example, the absorbing the function includes modifying contents of the memory based on the function of the arithmetic operator to provide an updated memory and removing the arithmetic operator from the circuit design.

Abstract: A method for generating physical design layout patterns includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one layer of the layers in a given one of the physical design layout patterns. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating synthetic three-dimensional arrays utilizing the generator neural network of the trained GAN, a given synthetic three-dimensional array comprising a set of two-dimensional arrays each representing features for a new layer of a new physical design layout pattern.

Abstract: Various embodiments provide for circuit design routing using a track assignment based on a plurality of panels (also referred to herein as a multi-panel track assignment). According to some embodiments, a track assignment of a wire within a particular panel is performed based on a primary panel bound or limit and a secondary panel bound or limit. For instance, during a track assignment for a particular wire falling within a particular panel, an embodiment can first attempt to assign the particular wire to a track that falls within panels within the primary panel bound and, if deemed not possible (e.g., due to a DRC, violation or congestion issue), the embodiment can then assign the particular wire to a track that falls within panels within the secondary panel bound.

Abstract: A method for detecting hotspots in physical design layout patterns includes receiving a given physical design layout pattern, utilizing a hotspot detection model to detect one or more potential hotspots in the given physical design layout pattern, and performing a verification to determine whether a given potential hotspot of the one or more potential hotspots detected by the hotspot detection model comprises a real hotspot or a nonexistent hotspot. The method also includes, responsive to determining that the given potential hotspot comprises an actual hotspot, modifying the given physical design layout pattern to remove the actual hotspot. The method further includes, responsive to determining that the given potential hotspot comprises a nonexistent hotspot, augmenting the hotspot detection model with additional training data generated based on the nonexistent hotspot.

Abstract: In some examples, a wireless charging system includes a pressure sensitive plate, a plurality of charging coils, and a base that includes one or more processors and logic instructions. The logic instructions are executable by the one or more processors to detect a device placed on the pressure sensitive plate, determine a location of the device on the pressure sensitive plate, identify one or more charging coils of the plurality of charging coils that are within a predetermined distance from the device, and activate the one or more charging coils without activating remaining charging coils of the plurality of charging coils. The one or more charging coils are sufficiently near a receiver located in the device to create inductive coupling with the receiver to charge a battery of the device.

Abstract: Disclosed herein is an apparatus that includes a first pair of signal lines and a second pair of signal lines. Each pair of signal lines comprises a first line and a second line that collectively signal any one of: a logical zero, a logical one, and nothing. A first cell occupies a first layer of the apparatus to receive the first line of the first pair of signal lines and the first line of the second pair of signal lines; and a second cell occupies a second layer of the apparatus to receive the second line of the first pair of signal lines and the second line of the second pair of signal lines. The first cell is a dual of the second cell and at least partially overlaps the second cell.

Abstract: A system and method to perform timing analysis in integrated circuit development involves defining an integrated circuit design as nodes representing components of the integrated circuit design that are interconnected by edges representing wires. Sequentially connected nodes define a path. Statistical variables are defined for a canonical delay model of each node and edge of the integrated circuit design and define a first set of conditions. The method includes performing a statistical static timing analysis to obtain an arrival time at each node as a sum of the canonical delay models for nodes and edges that precede the node in the path of the node, obtaining a projected arrival time at a second set of conditions for the node by scaling the arrival time for the node using scale factors that represent the second set of conditions and using a transformation matrix, and providing the integrated circuit design for fabrication.

Abstract: A system and method to perform capacitance extraction involves defining a location of signal wires and floating metal of an integrated circuit design. The method includes designating one of the signal wires as a target wire, defining a first area within which first capacitances between the target wire and the floating metal and other signal wires are determined, defining a second area, within which second capacitances between floating metal within the first area and the floating metal and the other signal wires not within the first area are determined, and generating an intermediate capacitive network. The intermediate capacitive network includes the target wire, the floating metal, and the other signal wires within the second area, the first capacitances and the second capacitances. A capacitive network is generated from the intermediate capacitive network. The first capacitances and the second capacitances are used to generate third capacitance values of the capacitive network.

Abstract: Technology is described for providing code modules for building a device. An indication of hardware components to be used when designing a device may be received. A use case for the device may be received. A list of code modules that are compatible with the hardware components may be provided. The list of code modules may be based on the use case for the device. A selection of code modules may be received from a list of code modules that are compatible with the hardware components. The code modules may be provided for use in designing the device.

Abstract: A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing electromigration (EM) information of the first circuit to determine if the first via pillar induces an EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: A system includes a door, an external electrical connection electrically coupled to a charge store, an opening assembly including a controller, an actuator, a gear, and an actuator arm. The actuator arm is mechanically coupled to the actuator and removably coupled to the door such that the actuator arm opens or closes the door upon actuation of the actuator and the external electrical connection electrically couples to a mobile robotic power delivery device that includes a battery to provide electrical power to the actuator and the controller.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.

Abstract: A method for determining a density of an integrated circuit layout includes analyzing the IC layout represented by polygons. A portion of the IC layout is analyzed within a sample window located at a sample point. A local density of polygons within the sample window is determined, where an area of one or more of the polygons within the sample window is weighted according to a weighting function giving unequal weight to polygon area based on a position within the sample window. The local density values at each sample point in an array of sample points can be used to determine a layout density and to identify locations of density violations.

Abstract: The disclosure enclosed herein discloses a gamepad, the gamepad comprising: a thimble contact rechargeable battery package, a battery cover, and a charging dock, wherein the dock comprises an upper cover, a bottom shell, and a charging PCB arranged between them. The disclosure has a dual-charge dock charging for two gamepads simultaneously, with two thimbles. A battery groove is at a back of the gamepad, and a battery cover matching the battery groove is provided therein, and also has a charging window. The rechargeable battery package has a charging interface and a discharging interface. When in use, the rechargeable battery package is placed into the battery groove and covered. The discharging interface is electrically connected to the gamepad, supplying power thereto. When being charged, the gamepad is placed on the charging dock; the thimble arranged at the charging dock contacts with the charging interface through the charging window to realize charging.