Patents Examined by Sun James Lin
  • Patent number: 7409651
    Abstract: A method for migrating an electronic circuit from a source technology to a target technology includes accepting a source circuit that operates in the source technology. The source circuit includes source components interconnected at nodes in accordance with a source topology. Source voltages at the nodes of the source circuit are determined, and the source voltages are transformed to produce respective target voltages suitable for the target technology. The source circuit is separated into sub-circuits, each sub-circuit including one or more of the source components. In each sub-circuit individually, the one or more of the source components are converted to one or more respective target components in the target technology responsively to the target voltages, so as to produce a respective migrated sub-circuit. The migrated sub-circuits are reconnected to produce a target circuit in the target technology, the target circuit having a target topology identical to the source topology.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: August 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Israel Berger, Kirill Dyagilev, Dov Ramm, Benjamin Sheinman, Oren Shlomo
  • Patent number: 7409654
    Abstract: A method, computer program product, and data processing system for minimizing the number of test sequences needed to achieve a desired level of coverage of events in testing a semiconductor design is disclosed. Test patterns are randomly generated by one or more “frontend” computers. Results from applying these patterns to the design under test are transmitted to a “backend” computer for processing. A determination is made as to which test sequences trigger events not already triggered by previously-considered test sequences. An autograde data structure is generated which further reduces the number of test sequences. A preferred embodiment of the present invention may be used to reduce the number of test sequences required, but may also be used to provide test engineers a basis for devising manually-created test sequences to test related events.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: August 5, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: George W. Wood, Amol V. Bhinge
  • Patent number: 7398509
    Abstract: A computer network for generating instructions for photomask manufacturing equipment, based on photomask specification data input by a customer. A series of order entry screens are downloaded to a remote customer's computer, typically via an internet connection. The customer is prompted to enter photomask specification data, which is delivered to computing equipment on the manufacturer's local network. The manufacturer's computing equipment validates the photomask specification data, and uses this data to generate fracturing instructions and equipment control instructions. The fracturing instructions, together with pattern design data from the customer, are delivered to a fracture engine, which provides fractured pattern data. The control instructions and the fractured pattern data may then be electronically delivered to the manufacturing equipment.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: July 8, 2008
    Assignee: Toppan Photomasks, Inc.
    Inventors: Jeffry S. Schepp, Jan E. Gentry, Thomas T. Cogdell
  • Patent number: 7398494
    Abstract: The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation aim; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: July 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Bodo Hoppe, Christoph Jaeschke, Johannes Koesters
  • Patent number: 7398493
    Abstract: A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are shorted to a substrate are detected. Node breakers are inserted in the layout between pwell isolation tanks coupled to the same node and between the substrate and isolated pwell tanks coupled to the substrate. The node breakers are inserted in the circuit schematic as well to satisfy a layout versus schematic comparison. Inserting the node breakers highlights circuit component groupings as well as which tanks contain certain elements, if any. This allows designers to make a conscious decision as to the location and groupings of elements in a layout design.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: July 8, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Haim Horovitz, Mark Allenspach, Peter Fleischmann
  • Patent number: 7398499
    Abstract: A method of searching paths that are susceptible to electrostatic discharge (ESD) at the beginning of an integrated circuit (IC) design is disclosed that includes a circuit spreading out algorithm, a matrix closure algorithm, and a supernode algorithm. The found paths are required to satisfy conditions including that (a) they are connected from a gate of a transistor to a source or a drain thereof, and (b) the head node and the tail node of each path are pins of a top level of the IC. ?1/0/1 matrix multiplication is employed by both the circuit spreading out algorithm and the matrix closure algorithm so as to obtain a result of node connections after a plurality of matrix self-multiplications.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: July 8, 2008
    Assignee: Chang Gung University
    Inventors: Ming-Hong Lai, Chao-Yi Cho, Chia-Chi Chu, Wu-Shiung Feng
  • Patent number: 7389482
    Abstract: A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a layout design. The tool filters, consolidates, and sorts the timing violations and presents the foregoing in a report of consolidated timing violations. The report of consolidated timing violations can then be analyzed by a verification engineer.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: June 17, 2008
    Assignee: Broadcom Corporation
    Inventors: Heather Bowers, Frank Huang
  • Patent number: 7380232
    Abstract: Method and apparatus for designing a system for implementation in a programmable logic device (PLD) is described. In one example, a program language description of the system is captured. The program language description includes control code for configuring actor elements with functions to perform tasks in response to input data. A hardware implementation is generated for the PLD from the program language description by mapping the control code to decision logic, the functions to partial configuration streams, and the actor elements to reconfigurable slots.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: May 27, 2008
    Assignee: Xilinx, Inc.
    Inventors: Paul R. Schumacher, Jorn W. Janneck, David B. Parlour
  • Patent number: 7376928
    Abstract: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: May 20, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Noriaki Matsuno, Masato Tsunoda, Hirofumi Wada
  • Patent number: 7373618
    Abstract: A system, method, computer program, and article of manufacture for generating a golden circuit including datapath components for equivalence checking of synthesized revised circuit. The method includes generating a set of static, dynamic and derived candidates for the datapath component subcircuit, evaluating the similarity degree for each candidate in relation to the revised circuits and selecting one candidate for implementation in the golden circuit. As a result, the subcircuit of datapath component in the golden circuit is replaced with the subcircuit which is more similar to the revised circuit to improve the efficiency of the equivalence checking.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: May 13, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kei-Yong Khoo, Tao Feng, Debjyoti Paul, Chih-Chang Lin
  • Patent number: 7370313
    Abstract: The invention relates to a method for optimizing a mask layout pattern comprising at least one structural feature. First a desired layout pattern is provided. Based on the desired layout pattern, an optimized reference diffraction coefficient is provided. After selecting an initial mask geometry having polygon-shaped structures, initial diffraction coefficients are calculated. A difference based on the reference diffraction coefficient and initial diffraction coefficients is used to optimize the initial geometry in order to provide a mask layout pattern.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: May 6, 2008
    Assignee: Infineon Technologies AG
    Inventors: Christoph Noelscher, Bernd Kuechler, Roderick Koehle
  • Patent number: 7367008
    Abstract: A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: April 29, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7363605
    Abstract: A method for analyzing a circuit design identifies a possible noise fault for a timing interval based on a timing analysis of a victim net and at least one aggressor net of the circuit design and determines whether the noise fault is feasible based on a behavioral representation of the victim net and the aggressor net for the timing interval.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: April 22, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alex Kondratyev, Kenneth Tseng, Yosinori Watanabe
  • Patent number: 7360182
    Abstract: A method and a system for reducing delay noise in an integrated circuit (IC) includes generating delay information for each net, and each device of the IC. Each net has a ground capacitance, a coupling capacitance, and a resistance. An effective capacitance is computed for each net. The effective capacitance is divided by sum of the ground capacitance and the coupling capacitance to compute a scale factor. The effective capacitance is then scaled by the scale factor to determine a delay noise induced load. Finally, the timing paths are optimized incrementally by using the delay noise induced load, the resistance, and the delay information.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: April 15, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Arijit Dutta, Bhuwan K Agrawal, Atul Dogra
  • Patent number: 7360187
    Abstract: A method and system for formally verifying designs having elements from more than a single design domain is described. An example system allows formal verification of a design containing mixed analog and digital subparts. The system may use different proof engines to solve an appropriate sub-partition of the entire design, and may provide a framework for translating between the different domains to create a unified result. For example, a digital proof engine may be used for a digital only subpart, while an analog proof engine may be used for an analog only subpart. The system may use the partitioning results to determine translators between the various domains, and an order in which the proof engines are applied.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: April 15, 2008
    Assignee: Rambus Inc.
    Inventors: Kevin D. Jones, Thomas J. Sheffler, Kathryn M. Mossawir, Qiang Hong, Paul Wong, Jing Jiang
  • Patent number: 7356795
    Abstract: A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: April 8, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Yamauchi
  • Patent number: 7356798
    Abstract: A method including receiving, for respective terminals, wiring enable/disable information which sets a region where a connection of a wiring line is enabled and a region where a connection of a wiring line is disabled, and storing the wiring enable/disable information, and determining, using the wiring enable/disable information, whether a connection of a wiring line to a predetermined portion of a terminal of an element is enabled, and when the connection of the wiring line is enabled, executing the connection, wherein the wiring enable/disable information sets wiring enable regions at two end portions of the terminal, sets a wiring disable region at a central portion of the terminal except the two end portions, and sets an interval between either end face of the terminal and another wiring line different in longitudinal direction from the terminal to a predetermined interval not smaller than a minimum interval defined by a design rule.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: April 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoyuki Tamura, Takayuki Kamei
  • Patent number: 7353470
    Abstract: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: April 1, 2008
    Assignee: On-Chip Technologies, Inc.
    Inventors: Laurence H. Cooke, Bulent I. Dervisoglu
  • Patent number: 7353472
    Abstract: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: April 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: David L. DeMaris, Timothy G. Dunham, William C. Leipold, Daniel N. Maynard, Michael E. Scaman, Shi Zhong
  • Patent number: 7353482
    Abstract: A layout editor apparatus draws line segments constituting a first interconnect line connecting between an output pin and a first input pin so as to draw the first interconnect line as a straight line formed of the line segments connected in a line extending from the output pin only in a first direction, and draws line segments constituting a second interconnect line connecting between a branch point and a second input pin so as to draw the second interconnect line as a straight line formed of the line segments connected in a line extending only in the first direction from a point that is displaced from the branch point on the first interconnect line in a second direction perpendicular to the first direction, wherein the displayed lengths of the line segments are proportional to their physical lengths, and the displayed widths of the line segments reflect their physical widths.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: April 1, 2008
    Assignee: Fujitsu Limited
    Inventor: Ikuko Murakawa