Abstract: In an exemplary layout structure of a semiconductor integrated circuit manufactured by a photolithographic process using an exposing light having a wavelength ?, a peripheral circuit region is formed by arranging a plurality of peripheral circuit cells, each having peripheral circuit patterns, along a side of an internal circuit region. A proximity dummy region is formed by arranging a plurality of proximity dummy cells, each having a proximity dummy pattern, along at least one side of the peripheral circuit region. The proximity dummy region includes a line-and-space repetition structure including, and having the regularity of, two or more pairs of lines and spaces between the lines every 8?. The repetition structure in the proximity dummy region reduces the dimensional deviation in the outermost portion of the peripheral circuit region.

Abstract: A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including 1) receiving the upper layout containing features and modifications to features, 2) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, 4) selecting a feature in the upper layout, 5) retrieving, from the density map, the geometry coverage of a sub-region below the feature, 6) determining a vertical deviation of the feature using the geometry coverage, 7) determining an alteration to the modification using the vertical deviation, 8) applying the alteration to the modification, and 9) repeating for all features. In some embodiments, the upper layout is designed using a library of pretabulated models, each model containing a modification to a feature calculated to produce a satisfactory feature on a wafer.

Abstract: It is intended to provide net list creating method, net list creating device, and computer program thereof capable of creating net list of memory space by selecting optimum combination of memory macros and providing a control circuit for controlling and making the combination accessible as memory space from a previously registered library so as to realize required memory space. For realizing a target memory with a single memory macro by extending its word width, processing goes on to as follows: target word width of a target memory is larger than maximum macro word width of a memory macro (S5: YES); first word width ratio (WR1), target word width to maximum macro word width, is 2n and first bit width ratio (BR1), bit width of a target memory to bit width of memory macro which has maximum macro word width, is 2(?n) or smaller (S9: YES); a memory macro which has maximum macro word width is selected (S11); and a control circuit is selected from a control library (D3) previously provided after branch a.

Abstract: Methods and apparatuses to automatically modify a circuit design according to the possible deviation in the subsequent implementation of the circuit. In one aspect, a method to design a circuit includes: determining whether a design constraint is likely to be violated during a subsequent routing implementation of a design of the circuit; and, modifying the design of the circuit to reduce likelihood of the design constraint being violated during a subsequent implementation. For example, a route for a net with a number of fanout larger than two and on a timing critical or near-critical path may be considered sensitive to route topology such that an alternative routing path may lead to a violation in timing constraint; to reduce the possibility of a timing problem in a subsequent routing solution, a transformation can be selectively applied to the circuit design to an extent not worsening a cost function.

Abstract: A controller arranges macrocells having power terminals and ground terminals in desired positions on a semiconductor chip. The power terminals and ground terminals are arranged in a fourth line layer such that the centers of square power terminals and ground terminals substantially coincide with lattice points, and terminals of different types are not mixed along the same row, for example. The controller then forms an orbital power ring, performs terminal processing of the chip internal power line, retrieves from the terminal information library the defined position of a single terminal in each row from among the power terminals and ground terminals, and identifies the position as that of a terminal to be connected.

Abstract: A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input.

Abstract: A method for the synthesis of multi-level combinational circuits with cyclic topologies. The techniques, applicable in logic synthesis, and in particular in the structuring phase of logic synthesis, optimize a multi-level description, introducing feedback and potentially optimizing the network.

Abstract: An embodiment of the invention is a logic minimization method that provides improved user design performance without a substantial increase in user design area. Alternate factorizations are determined for portions of the user design. For each factorization, a delay metric is computed. The user design is optimized by selecting factorizations based on a balance of performance and area considerations. The optimized design is then mapped to the hardware architecture of the programmable device. A first portion of the user design is mapped to maximize performance, while a second portion of the user design is mapped to minimize area. The first portion of the user design includes a set of data paths each having a delay metric above a delay threshold. The delay metric can be derived from a unit delay computation or from timing analysis.

Abstract: A system on chip (SOC) is provided according to an embodiment of the invention. The SOC includes a storage system, a network on chip (NOC) adapted to communicate with a communication network, and a processing system in communication with the storage system and with the NOC. The processing system is configured to conduct operations of the SOC and perform communication operations using the NOC. The SOC further includes an integrated test processor (ITP) in communication with the processing system, the storage system, and the NOC. The ITP is configured to generate a logical function test instruction for testing one or more logical functions of the SOC and generate a physical link test instruction for testing one or more physical links of the SOC.

Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces a large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance memos to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.

Abstract: A system is provided to aid in laying out circuits on a semiconductor wafer, in which a wafer map is automatically generated when entering chip sizes, arrangements and other enterable factors, with a goal to maximize yield probability. The subject system accommodates different chip types and arrangements within a wafer map and addresses edge exclusion, utilization of chiplets and accommodation of different centering techniques, including a variety of ways of measuring offsets, while outputting a display of replicated circuits on the wafer as well as chip count and density, utilizing a portable, tailorable, extendable PC-based program featuring an easy-to-use graphical interface. The software application provides a user with different graphical views customized for different process areas, such as lithography and dicing, with the application being useful for any semiconductor manufacturing facility, foundry or similar industry that needs to generate wafer maps automatically to maximize yield probability.

Abstract: A method for performing a voltage drop analysis in a logic circuit that takes into consideration voltage drop—current drain dependency. The voltage drop analysis helps in accurately estimating power requirements of the logic circuit, designing optimal power grids and performing accurate static timing analysis for the logic circuit. The logic circuit has a plurality of gates. The method generates polynomial models for the power consumption, delay and transition time of each gate in the logic circuit. Thereafter, the polynomial models are solved to determine the supply voltage available at each gate of the logic circuit. The supply voltage, thus determined, is used to perform voltage drop analysis.

Abstract: An apparatus, system, method, and program for facilitating the design of a bare board circuit board include transmitting a user interface application to a user over a publicly-accessible global network. The user interface application is updated in response to circuit board design data entered by the user.

Abstract: An integrated circuit and a method for using metal fill geometries to reduce the voltage drop in power meshes. Metal fill geometries are connected to the power mesh using vias or wires at multiple locations. Metal fill geometries are connected to other floating metal fill geometries using vias or wires at multiple locations. The circuit design introduces maximum redundancy between metal fill geometries and power mesh geometries, but partial redundancy between metal fill geometries and metal fill geometries. In particular, the redundancy in connectivity between metal fill geometries and metal fill geometries is kept minimal to reduce the number of geometries introduced. The high redundancy between metal fill geometries and power mesh geometries and the partial redundancy among metal fill geometries result in a smaller IR-drop by reducing the effective resistance on a power mesh.

Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.

Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.

Abstract: A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Each decoupling capacitor cell has a width, which is greater than that of a single base cell location and which is abstracted from the base layer layout pattern. A cell library defines a plurality of cells, including a macro cell having open rows consistent with the rows in the base layer layout pattern that are reserved for the decoupling capacitor cells. The width of each decoupling capacitor cell is abstracted from the macro cell. Cells from the cell library, including the macro cell, are placed within a design layout pattern relative to the base layer layout pattern. An area consumed by the macro cell within the design layout pattern is independent of the width of the decoupling capacitor cells.

Abstract: A method and computer program for generating a capacitance value rule table, which simplifies generation of the capacitance value rule table for multilayer wiring having a complex dielectric constant structure are provided. In the method, construction data of wire adjacent to a wire of interest is extracted (S30), a common dielectric constant for a plurality of insulating film in the construction data is calculated (S32), and capacitance value rule table (F12) is created based on the common dielectric constant (s34).

Abstract: A method of automatically correcting mask pattern data includes steps (a) to (d). Here, in this method, the mask pattern data are for producing photo masks used in manufacturing processes of a semiconductor integrated circuit where cells including dummy cells are placed on a semiconductor chip. The step (a) is a process of merging tentatively an assistant mask layer into one of main mask layers. Each of the main mask layers corresponds to one of the photo masks. The assistant mask layer includes first regions, each of which corresponds to one of the dummy cells. The step (b) is a process of checking whether or not the one of main mask layers and the merged assistant mask layer agree with a design rule. The step (c) is a process of replacing the one of main mask layers with another of the main mask layers, into which the assistant mask layer is merged, when a violation against the design rule is found in the step (b).

Abstract: A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.