Patents Examined by Sung Cho
  • Patent number: 10332584
    Abstract: The present invention is provided with; subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Noriaki Mochida
  • Patent number: 10332591
    Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: William V. Huott, Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu
  • Patent number: 10325649
    Abstract: A ternary sense amplifier and an SRAM array realized by the ternary sense amplifier are provided. The ternary sense amplifier comprises the 1st CNFET transistor, the 2nd CNFET transistor, the 3rd CNFET transistor, the 4th CNFET transistor, the 5th CNFET transistor, the 6th CNFET transistor, the 7th CNFET transistor, the 8th CNFET transistor, the 9th CNFET transistor, the 10th CNFET transistor, the 11th CNFET transistor, the 12th CNFET transistor and the 13th CNFET transistor; the SRAM array comprises a ternary sense amplifier, a ternary memory array, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 14th CNFET transistor, the 15th CNFET transistor, the 16th CNFET transistor, the 17th CNFET transistor, the 18th CNFET transistor and the 19th CNFET transistor; it features in low power consumption, less postponement and high yield of chips.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 18, 2019
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Daohui Gong, Yaopeng Kang, Huihong Zhang
  • Patent number: 10317922
    Abstract: A power supply management circuit manages transfer of power that is supplied to a peripheral device from a power supply device. The power supply management circuit includes a current limiter and one or more capacitors. The current limiter limits intensity of first current received from the power supply device through an input terminal to be smaller than or equal to limitation intensity, and outputs second current having intensity limited to be smaller than or equal to the limitation intensity through an output terminal connected to the peripheral device. When the intensity of the first current exceeds the limitation intensity, the capacitors output third current through the output terminal.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Iksung Park, Heeyoub Kang, Kyoungeun Lee
  • Patent number: 10269406
    Abstract: A memory device, such as an FeDRAM device, includes a memory array including a plurality of rows, each row having a plurality of storage elements (e.g., FeFETs). The memory device further includes a plurality of refresh trigger circuits, each refresh trigger circuit being associated with a respective one of the rows. Each refresh trigger circuit is structured to produce an output signal indicative of an estimated degradation of a memory window of one or more of the storage elements of the associated one of the rows. The memory device also further includes control circuitry coupled to each of the refresh trigger circuits, wherein the control circuitry is structured and configured to determine whether to initiate a refresh of the storage elements of a particular one of the rows based on the output signal produced by the refresh trigger circuit associated with the particular one of the rows.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 23, 2019
    Assignee: University of Pittsburgh—Of the Commonwealth System of Higher Education
    Inventors: Ismail Bayram, Yiran Chen
  • Patent number: 10269409
    Abstract: A non-volatile semiconductor memory device and a driving method for word lines thereof are provided. A flash memory of the invention includes a memory cell array including blocks and a block selection element selecting the block of the memory cell array based on row address information and including a block selection transistor, a level shifter, a boost circuit and a voltage supplying element. The block selection transistor is connected to each word line of the block. The level shifter supplies a voltage to a node connected to a gate of the block selection transistor. The boost circuit boosts a potential of the node. The voltage supplying element supplies an operation voltage to one of the terminals of the block selection transistor. The node, after performing first boosting by the operating voltage supplied by the supplying element, performs second boosting by the second circuit.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: April 23, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Hiroki Murakami
  • Patent number: 10262720
    Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 16, 2019
    Assignee: Renesas Electroncis Corporation
    Inventor: Koji Nii
  • Patent number: 10262717
    Abstract: The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 16, 2019
    Assignee: Invensas Corporation
    Inventors: David Edward Fisch, William C. Plants
  • Patent number: 10262714
    Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: April 16, 2019
    Assignee: The Penn State Research Foundation
    Inventors: Sumeet Kumar Gupta, Ahmedullah Aziz, Nikhil Shukla, Suman Datta, Xueqing Li, Vijaykrishnan Narayanan
  • Patent number: 10249361
    Abstract: A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: April 2, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Eugene Wang, Gavin Chen, Demi Shen
  • Patent number: 10217497
    Abstract: A memory device includes a delay locked loop (DLL) circuit to receive an external clock, and delay the external clock by a DLL delay time to provide a DLL clock, an output driver to output the DLL clock as a data strobe signal, and a DLL offset control circuit configured to receive at least one of a plurality of functional statement commands, and adjust the DLL delay time based on the at least one of the functional statement commands. Each one of the DLL circuit and the output driver is selectively powered according to the at least one of the functional statement commands.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 26, 2019
    Assignee: Winbond Electronics Corporation
    Inventor: Myung Chan Choi
  • Patent number: 10176881
    Abstract: A non-volatile memory device includes: a memory cell array including a memory cell string including a ground selection transistor and a plurality of serially connected non-volatile memory cells; a ground selection line connected to the ground selection transistor and a plurality of word lines connected to the plurality of memory cells; a voltage generator configured to generate a program verification voltage and a read voltage applied to the plurality of word lines; and a control circuit configured to control a compensation for the program verification voltage based on a program verification temperature offset, and control a to compensation for the read voltage based on a read temperature offset.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jisuk Kim, Il Han Park, Se Hwan Park
  • Patent number: 10175948
    Abstract: A system according to one embodiment includes a pinned layer; a spacer layer above the pinned layer; a free layer above the spacer layer; a heating device, for heating the free layer to induce a paramagnetic thermal instability in the free layer whereby a magnetization of the free layer randomly switches between different detectable magnetic states upon heating thereof; and a magnetoresistance detection circuit for detecting an instantaneous magnetic state of the free layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: January 8, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Patrick M. Braganca, Jordan A. Katine, Yang Li, Neil L. Robertson, Qingbo Wang, Haiwen Xi
  • Patent number: 10176865
    Abstract: An integrated circuit comprising at least one logic tile, wherein at least one logic tile includes a mesh interconnect network. The mesh network includes (i) a plurality of interconnected multiplexers, wherein each multiplexer includes inputs, an output, and a plurality of selection inputs to receive signals that control whether an input is connected to the output and (ii) an inactive/static multiplexer which includes inputs, an output that is inactive/static, and a plurality of selection inputs to receive signals that control whether an input of the inactive/static multiplexer is connected to the output wherein such output is connected to an input of at least one of the interconnected multiplexers of the mesh network. In operation, the selection signals applied to the selection inputs of the inactive/static multiplexer are programmed to concurrently connect two or more inputs to the output of the inactive/static multiplexer.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: January 8, 2019
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 10163493
    Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: William V. Huott, Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu
  • Patent number: 10156482
    Abstract: A semiconductor chip temperature estimation device that estimates the temperature of a semiconductor chip incorporated together with a thermistor in a semiconductor module includes a first estimation unit which calculates a first estimation value of a chip loss of the chip, a memory which stores in advance a correlation between a temperature rise of the temperature sensor and the chip loss of the chip, a second estimation unit which calculates a second estimation value of the temperature rise of the temperature sensor, and a third estimation unit which calculates a third estimation value of the temperature of the cooling element. The temperature of the semiconductor chip is estimated by using the third estimation value as a base temperature.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: December 18, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akihiro Imakiire, Akihiro Odaka, Shinichiro Adachi
  • Patent number: 10147496
    Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh Gautam, Suresh Uppal, Min-hwa Chi
  • Patent number: 10134979
    Abstract: A spintronic device is disclosed. The spintronic device includes a spin current transport layer, a spin injector, and a spin detector. The spin injector includes a first tunnel barrier layer made of strontium oxide (SrO) disposed over the spin current transport layer and a first magnetic material layer disposed over the first tunnel barrier layer. The spin detector includes a second tunnel barrier layer made of SrO disposed over the spin current transport layer. A second magnetic material layer is disposed over the second tunnel barrier layer and a spin sensor has a sensor input terminal coupled to the second magnetic material layer.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: November 20, 2018
    Assignee: Ohio State Innovation Foundation
    Inventors: Roland K. Kawakami, Simranjeet Singh, Jyoti Katoch
  • Patent number: 10074406
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10049765
    Abstract: A dynamic random access memory (DRAM) has a main memory cell array and a redundant component unit. The redundant component unit includes a plurality of e-fuses and a latch region. The plurality of the e-fuses are arranged into a first e-fuse part and a second e-fuse part, wherein the first e-fuse part is used to store address information of a fault memory cell in the main memory cell array and the second e-fuse part is used as a plurality of capacitors. The latch region includes a plurality of latches used to store the address information of the fault memory cell stored in the first e-fuse part, wherein the plurality of the capacitors of the second e-fuse part are respectively coupled to the plurality of the latches to provide a capacitance value for an input/output (I/O) endpoint of each of the latches.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 14, 2018
    Assignees: United Microelectronics Corp., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai