Abstract: A dynamic random access memory (DRAM) has a main memory cell array and a redundant component unit. The redundant component unit includes a plurality of e-fuses and a latch region. The plurality of the e-fuses are arranged into a first e-fuse part and a second e-fuse part, wherein the first e-fuse part is used to store address information of a fault memory cell in the main memory cell array and the second e-fuse part is used as a plurality of capacitors. The latch region includes a plurality of latches used to store the address information of the fault memory cell stored in the first e-fuse part, wherein the plurality of the capacitors of the second e-fuse part are respectively coupled to the plurality of the latches to provide a capacitance value for an input/output (I/O) endpoint of each of the latches.

Abstract: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.

Abstract: A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.

Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

Abstract: A method includes: during a read operation of a first storage node and a second storage node formed by cross-coupled inverters, based on data stored in the first storage node and the second storage node, causing a first auxiliary branch or a second auxiliary branch to assist a corresponding one of the cross-coupled inverters in holding data; and during a write operation of the first storage node and the second storage node, based on data to be written to the first storage node and the second storage node, causing the first auxiliary branch or the second auxiliary branch to assist a corresponding one of the cross-coupled inverters in flipping data.

Abstract: Disclosed are methods, systems and devices for powering up devices including non-volatile memory elements in an array of non-volatile memory elements. In one aspect, during a sequence for powering up an integrated device, non-volatile memory elements may be isolated from voltage supplies to avoid in advertent changes of memory states stored in the non-volatile memory elements.

Abstract: An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.

Abstract: Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.

Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.

Abstract: A memory circuit includes plurality of bit-cells organized in a column, each bit-cell of the plurality is coupled to a first voltage supply terminal and a second voltage supply terminal. A word-line control circuit is coupled to each bit-cell of the plurality by way of a local bit-line. The word-line control circuit is configured to operatively couple the local bit-line with a global bit-line during a read operation. A first voltage generation circuit is coupled to the first voltage supply terminal. The first voltage generation circuit is configured to provide a first reduced voltage at the first voltage supply terminal during a first write operation. A second voltage generation circuit is coupled to the second voltage supply terminal. The second voltage generation circuit is configured to provide a second reduced voltage at the second voltage supply terminal during the first write operation.

Abstract: A computing system for accessing a dynamic random access memory (DRAM) includes a processing circuit, a queue, and a DRAM controller. The processing circuit is configured for issuing an early notification signal before issuing a clock frequency switch signal; the early notification signal notifies upcoming of the clock frequency switch signal and the clock frequency switch signal requests a change of frequency of a DRAM clock. The queue has N entries and each entry stores at least an address and an associated command to be sent to the DRAM. The DRAM controller is configured for controlling access to the DRAM and the DRAM controller manages to decrease occupancy of the queue to a target level upon receiving the early notification signal.

Abstract: A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.

Abstract: A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells and a plurality of MOSFETS. The MOSFETs are controlled by a control signal to be in one of an active state or a standby state. Part of the MOSFETs are arranged along one end of the memory array and the other parts of the MOSFETs are arranged along another end of the memory array. The other end of the memory array is opposite to the one end of the memory array. The MOSFETs are controlled by the control signal to be turned ON in the active state and to be turned OFF in the standby mode.

Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.

Abstract: Methods and systems for verifying two or more programming states at the same time are described. During a program verify operation, two or more memory cell threshold voltage levels may be concurrently verified by applying a word line voltage to a plurality of memory cells, applying two or more different bit line voltages to the plurality of memory cells, and sensing the plurality of memory cells while the two or more different bit line voltages are applied to the plurality of memory cells. The bit line voltages applied during the program verify operation may allow a first set of the plurality of memory cells to be sensed at a first voltage level while a second set of the plurality of memory cells are sensed at a second voltage level different from the first voltage level.

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

Abstract: The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.