Abstract: Technical solutions are described for controlling operation of an electric machine such as a permanent magnet synchronous motor (PMSM) drive or motor control system to limit battery current and protect a battery from excessive discharging or charging current from the PMSM drive. Systems and methods employ a torque control algorithm for PMSMs that uses a battery current limit constraint when generating current commands during each of a maximum torque per ampere (MTPA) operation, and maximum torque per voltage (MTPV) operation. Torque search operations are performed in each of the MTPA and MTPV operation regions in a PMSM drive system until current commands are achieved under a given battery current limit constraint and while maintaining maximum voltage utilization throughout all PMSM operation regions.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a sensing node, a bit line controller connected between the sensing node and a bit line. The bit line controller is configured to first precharge and second precharge the sensing node.

Abstract: According to an exemplary embodiment, a display device comprises: a display panel configured to include a plurality of pixels; a printed circuit board connected to the display panel; a connector mounted in the printed circuit board; and a cable fastened to the connector, wherein the connector comprises: a first connector mounted in the printed circuit board to include a first voltage pad, a second voltage pad, and a plurality of signal pads disposed between the first voltage pad and the second voltage pad; a hinge engaged with the first connector; and a second connector for rotation with respect to a hinge shaft, the second connector includes a third voltage pad and a fourth voltage pad, wherein the cable is inserted between the first connector and the second connector.

Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.

Abstract: A motor driver includes a low-side drive transistor, a comparator, a sense transistor, first switch, and a second switch. The low-side drive transistor is adapted to be coupled to a motor. The comparator is configured to determine a direction of a drive current flowing in the low-side drive transistor. The sense transistor is coupled to the low-side side drive transistor and is configured to pass a replica of the drive current. The first switch is configured to couple the sense transistor to the low-side drive transistor responsive to the drive current flowing in a first direction through the low-side drive transistor. The second switch is configured to couple the sense transistor to a ground responsive to the drive current flowing in a second direction, that is opposite the first direction, through the low-side drive transistor.

Abstract: A semiconductor package is provided and includes: an insulative layer having opposing first and second surfaces; a wiring layer embedded in the insulative layer and having a first side that is exposed from the first surface of the insulative layer and a second side opposing the first side and attached to the second surface of the insulative layer; at least one electronic component mounted on the second side of the wiring layer and electrically connected to the wiring layer; and an encapsulating layer formed on the second side of the wiring layer and the second surface of the insulative layer and encapsulating the electronic component. Therefore, the single wiring layer is allowed to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path.

Abstract: A solar cell module and a method for manufacturing the same are discussed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate and first and second electrodes, each of which has a different polarity and is extended in a first direction on a back surface of the semiconductor substrate, and a plurality of conductive lines extended in a second direction crossing the first direction on the back surface of the semiconductor substrate, connected to one of the first and second electrodes through a conductive adhesive, and insulated from the other electrode by an insulating layer. The conductive adhesive includes a first adhesive layer connected to the one electrode and a second adhesive layer positioned on the first adhesive layer and connected to the plurality of conductive lines.

Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

Abstract: A semiconductor memory device includes a memory cell array, a page buffer, a control logic, and a voltage generator. The memory cell array includes memory cells. The page buffer is connected to the memory cells through a bit line and configure to read data of the memory cells. The control logic generates control signals for controlling the page buffer. The voltage generator generates activation voltages of the control signals. The page buffer includes a first transistor between the bit line and a first node, a second transistor between a power voltage and a second node, a third transistor between the first node and the second node, a fourth transistor between the second node and a third node, and a fifth transistor between the first node and the third node. The voltage generator controls a first control signal controlling the fifth transistor based on temperature of the semiconductor memory device.

Abstract: A word line decoding circuit and memory comprises a first address decoding module to obtain word line logic signals; a word line pre-coding module to obtain word line pre-coding signals and first switch signals; a second address decoding module to obtain first and second selection signals; a third address decoding module to obtain third selection signals; a first level conversion module which performs level conversion on the first selection signals to obtain first and second control signals; a second level conversion module which performs level conversion on the second selection signals to get third and fourth control signals; a third level conversion module which performs level conversion on the third selection signals to obtain fifth control signals; a word line toggle switch signal generation module which generates second switch signals based on each control signal; and a word line toggle module to generate word line signals.

Abstract: In a battery heating system an inverter includes a first-phase bridge arm, a second-phase bridge arm and a third-phase bridge arm connected in parallel, each of a upper bridge arm and a lower bridge arm is provided with a switch module, the switch module is connected in parallel with a buffer module; and a motor controller in the inverter is provided for providing driving signals to the switch module of a target upper bridge arm and the switch module of a target lower bridge arm to control the switch module of the upper bridge arm of any bridge arm among the three phases of bridge arms and the switch module of the lower bridge arm of at least one bridge arm among the bridge arms except the bridge arm where the switch module of the target upper bridge arm is located to be periodically turned on and off.

Abstract: A hybrid solar thermal and photovoltaic panel based cogeneration system and heat pump and non-tracking non-imaging solar concentrator based CSP stabilized power generation system comprises a hybrid solar thermal and photovoltaic panel based cogeneration subsystem to cogenerate electricity and heat, a heat pump subsystem to raise the temperature of the cogenerated heat, a non-tracking non-imaging solar concentrator based CSP subsystem to further upgrade the cogenerated thermal energy, a thermal storage to store the cogenerated heat, and a thermal power regeneration system, to take the stored cogenerated heat to regenerate power. The power output of the cogeneration subsystem supplemented with the power output from the thermal power regeneration system realizes stabilized power output.

Abstract: An air conditioner includes a compressor to compress a refrigerant used in a refrigeration cycle, a converter to generate DC voltage, an inverter to generate three-phase AC voltage from the DC voltage, a motor to generate driving force to drive the compressor by using a plurality of coils to which the three-phase AC voltage is applied, a connection switching unit to switch connection states of the plurality of coils, and an outdoor control device to control the connection switching unit. The outdoor control device restricts the switching of the connection states when a switching count of the connection states exceeds a count threshold value.

Abstract: A drain cleaning machine includes a brushless direct current (DC) motor configured to rotate a snake about the snake axis. An electronic processor is configured to control power switching elements to drive the brushless DC motor. In a first operating range when a load experienced by the brushless DC motor is less than or equal to a predetermined load, the electronic processor is configured to control the power switching elements to drive the brushless DC motor at an approximately constant speed regardless of the load experienced by the brushless DC motor. In a second operating range when the load experienced by the brushless DC motor is greater than the predetermined load, the electronic processor is configured to control the power switching elements to drive the brushless DC motor at a decreasing speed as the load experienced by the brushless DC motor increases.

Abstract: A method for a pre-lockout read for a reverse order read operation with lockout mode is disclosed. The method comprises: performing a pre-lockout read at a first sensing level to determine which memory cells of the set of memory cells are on in response to the first sensing level being applied to a selected word line; performing a first sensing operation on the selected word line at a second sensing level including sensing memory cells of the set of memory cells determined to be off in response to the pre-lockout read; and performing a second sensing operation on the selected word line at a third sensing level including sensing memory cells of the set of memory cells determined to be on in response to the pre-lockout read, where the first sensing level is of a value between the second sensing level and the third sensing level.

Abstract: A semiconductor memory device, and a method of operating the same, includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells, each storing N bits of data. The peripheral circuit performs a program operation on a physical page including selected memory cells. The peripheral circuit is configured to receive pieces of data of N logical pages and program the pieces of data of the N logical pages to the physical page based on a logic code. The logic code is determined to equalize numbers of sensing operations required to read the pieces of data of the N logical pages. Weak read levels are assigned, using the logic code, to read data of a logical page for which the number of sensing operations is smallest.

Abstract: The present disclosure relates to a NOR flash memory circuit, a data writing method, a data reading method, and a data erasing method. The NOR flash memory circuit includes: a NOR memory array, a source voltage selection unit, a well voltage selection unit, a word line gating unit, a bit line gating unit, a data reading unit, and an analog voltage generating unit. During data writing, a source is floated, and a well electrode is connected to ground; and a first forward voltage is applied to a bit line where a memory cell to be written data into is located, and a second forward voltage is applied to a word line where the memory cell to be written data into is located. During data reading, a source is grounded, and well electrodes are grounded; and a third forward voltage is applied to a word line.

Abstract: Embodiments disclosed herein include modular electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first connector module having a notch on a first end and a plurality of surface mount technology (SMT) pads on a second end. In an embodiment, the electronics package further comprises a second connector module having a keyed connector on a first end and a plurality of SMT pads on a second end. In an embodiment, the electronics package further comprises a system in package (SIP) module between the first connector module and the second connector module, the component module electrically and mechanically coupled to the SMT pads of the first connector and the SMT pads of the second connector.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory elements configured to store a plurality of weights and to be controlled according to a plurality of input signals respectively and a bit line coupled to the plurality of nonvolatile memory elements; and a computation output circuit configured to generate a computation signal corresponding to an inner product between an input vector corresponding to the plurality of input signals and a weight vector corresponding to the plurality of weights.

Abstract: Solar tracker systems include a torque tube, a column supporting the torque tube, a solar panel attached to the torque tube, and a damper assembly. The damper assembly includes an outer shell surrounding an inner shell. A piston is at least partially positioned within the inner shell and moveable relative thereto. An active lock of the damper assembly includes a housing positioned within the outer shell. The housing defines a cavity and a housing channel extending from the cavity to an outer fluid channel. A shaft extends into the cavity and a valve assembly is attached to the shaft. The shaft is rotatable within the cavity between an unsealed position in which the housing channel is in fluid communication with the cavity, and a sealed position in which the valve assembly is rotationally aligned with the housing channel and obstructs fluid communication between the cavity and the housing channel.