Abstract: A controller optimizes a read threshold value for a memory device using model-less regression. The controller performs read operations on cells using read threshold voltage values. The controller measures probability values for the multiple read threshold voltage values, and estimates a threshold voltage distribution curve based on the multiple read threshold voltage values and the measured probability values using a set regression formula. The controller determines a read threshold voltage value corresponding to a set point on the threshold voltage distribution curve, and performs a read operation on the cells using the read threshold voltage value.

Abstract: A printed circuit board with a lateral metallization groove and a processing method thereof, relates to the field of printed circuit boards with lateral metallization grooves, processing technologies thereof and batch processing methods. The processing method includes the following steps: step S01, drilling and milling grooves; step S02, performing metallization treatment; step S03, laying an outer layer circuit; step S04, performing pattern plating; step S05, performing first milling grooves; step S06, etching an outer layer; step S07, performing surface treatment after performing solder resist printing and character printing; step S08, forming to mill off connections of a processing side; step S09, performing second milling grooves to form a through groove. The present disclosure can implement: a long side of the printed circuit board can be directly connected with the ground wire rather than independently installing the ground wire; a small space is occupied and conveniently replacement.

Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.

Abstract: The present disclosure is related to a power module power structure and an assembling method thereof. The power module structure includes a first printed-circuit-board (PCB) assembly, a second PCB assembly, and a conductive connection component. The first PCB assembly includes a first circuit board, a power switch and a magnetic component. The first circuit board includes a first side, a second side and a through hole. The power switch is disposed on the first circuit board. The magnetic component includes a first magnetic core and a second magnetic core fastened on the first circuit board through the through hole. The second PCB assembly includes a second circuit board having a third side, a fourth side and a hollow slot passing therethrough. The second magnetic core is exposed through the hollow slot. The conductive connection component is disposed and electrically connected between the first PCB assembly and the second PCB assembly.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.

Abstract: A display module and an electronic device are provided. The display module includes a substrate, a display part, a driving chip, a flexible circuit, and a buffer part. The substrate includes a soldering portion. The display part is disposed on a light emitting side of the substrate. The driving chip is disposed on a light emitting side of the soldering portion. The flexible circuit board is bent from a first surface of the soldering portion to a second surface of the soldering portion. The buffer part is disposed between the flexible circuit board and the soldering portion.

Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals is the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.

Abstract: Methods, systems, and computer program products for user-preference driven control of electrical and thermal output from a photonic energy device are provided herein. A system includes a solar photovoltaic module, and a fluid positioned on the solar photovoltaic module. The system also includes configurable reflective surfaces that collect and distribute direct solar and diffuse solar radiation across multiple portions of the fluid and/or portions of the solar photovoltaic module. Additionally, the reflective surfaces is physically connected to the solar photovoltaic module at an angle that is variable in relation to the surface of the solar photovoltaic module. Further, the system includes a controller that modulates an amount of thermal output and/or electrical power output generated by the solar photovoltaic module by transmitting a signal to adjust at least one variable pertaining to the fluid, and transmitting a signal to adjust at least one variable pertaining to the reflective surfaces.

Abstract: According to one embodiment, a solar cell includes a first electrode, a second electrode, and a photoelectric conversion layer disposed between the first electrode and the second electrode. When a transmittance of the solar cell is measured in a wavelength range of 700 to 1000 nm, an average of the transmittance of the solar cell is 60% or more.

Abstract: A circuit board is installed with a semiconductor module on an upper face and provided with connection terminals on a lower face. A connection pin is provided on at least some of the connection terminals. The connection terminals include a drive terminal for driving the semiconductor module and a function terminal for connecting the semiconductor module and other function units. The disposition of the drive terminal in each of divided areas is point-symmetric with respect to a center of the circuit board. The divided areas divide the circuit board into fourths.

Abstract: A module (101) includes a substrate (1) having a main surface (1a) and a conductor column (4) disposed on the main surface (1a). The conductor column (4) includes a conductor column body (4a) and an overhanging part (4b) overhanging from an outer periphery of the conductor column body (4a) in a middle of a height direction of the conductor column body (4a).

Abstract: A solar cell panel can include a solar cell; a sealing member for sealing the solar cell; a first cover member disposed on the sealing member at one side of the solar cell; and a second cover member disposed on the sealing member at another side of the solar cell, in which the first cover member includes a base member and a colored portion having a light transmittance lower than a light transmittance of the base member, the first cover member constituting a colored area, and the colored portion includes at least two layers each formed of an oxide ceramic composition and having different colors or different light transmittances.

Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

Abstract: A memory system is provided to include a memory device and a memory controller configured to control the memory device. The memory device includes a first data latch storing information about a state of the memory cell and is configured to: execute a first verification operation and a second verification operation on the memory cell in response to receiving, from the memory controller, a suspend command to suspend a program operation being performed on the memory cell; store, in the first data latch, a temporary value obtained based on a result value of the first verification operation and a result value of the second verification operation; and execute, a resumption command to resume the program operation, a third verification operation, and restore the result value of the first verification operation and the result value of the second verification operation.

Abstract: A disconnect device includes a mounting plate having a thermally conductive substrate applied onto the mounting plate. A first layer of an electrically conductive material is applied onto the substrate. A semiconductor switch supported on the first layer connects or disconnects an input power source to or from a load. A second layer of an electrically conductive material applied onto the substrate is electrically isolated from the first layer. An electronic sensing, control and protection circuit is supported on the second layer and is connected to the semiconductor switch to control operation of the semiconductor switch. A control unit in communication with the electronic sensing, control and protection circuit via an electrically isolated control path provides control and communication between the electronic sensing, control and protection circuit and the semiconductor switch.

Abstract: A memory device comprising a memory array; and controller circuitry to apply a first pass voltage to a first plurality of unselected wordlines of the memory array during a string current sensing phase; and reduce the first pass voltage applied to the first plurality of unselected wordlines during a multistrobe sensing phase that follows the string current sensing phase.

Abstract: A nanopore device includes an aperture and an electrode pair. A transimpedance amplifier converts a current signal IS that flows through the nanopore device into a voltage signal VS. The nanopore device measures small particles based on first data obtained by removing a DC component from the voltage signal VS and second data obtained based on the voltage signal VS from which the DC component has not been removed. Furthermore, the nanopore device is capable of monitoring the state of the nanopore device.

Abstract: A battery includes an anode; an electrolyte including an oxidizing gas; a metal halide that functions as an active cathode material; and a solvent including a nitrile compound; and a current collector contacting the cathode material.

Abstract: A continuous reading method of a flash memory is provided, including: after outputting data held in a cache memory (C0) of a latch (L1) of a page buffer/sensing circuit, data of the cache memory (C0) of a next page is read from a memory cell array, and the read data of the cache memory (C0) is held in the latch (L1). After outputting data held in the cache memory (C1) of the latch (L1), data of the same next page of the cache memory (C1) is read from the memory cell array, and the read data of the cache memory (C1) is held in the latch (L1).

Abstract: A semiconductor device package includes a first passive component having a first surface and a second passive component having a second surface facing the first surface of the first passive component. The first surface has a recessing portion and the second surface includes a protruding portion within the recessing portion of the first surface of the first passive component. A contour of the protruding portion and a contour of the recessing portion are substantially matched. A method of manufacturing a semiconductor device package is also disclosed.