Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

Abstract: Semiconductor devices and systems are disclosed. A semiconductor device includes a redistribution layer including a first polygonal structure for conveying a first power signal and including a first cutout region. The semiconductor device further includes a second polygonal structure for conveying a second power signal. Further, the semiconductor device includes an island polygon for conveying a third power signal and positioned within the first cutout region, wherein the island polygon does not touch the first polygonal structure.

Abstract: Systems and devices for enabling the use of SIP subsystems to make a configurable system having a unique interconnecting scheme creates appropriate connections between the SIP components and/or subsystems such that desired characteristics and features for the configurable system are provided.

Abstract: An electrical node includes a substrate for accommodating a functional element. The substrate includes a first side and an opposite second side, and hosting a number of connecting elements. The functional element includes an electronic component and conductive traces. The electrical node also includes a first material layer defining a protective covering. The first material layer defining at least a portion of the exterior surface of the nod arranged to reduce at least thermal expansion and/or mechanical deformation related stresses between one or more elements included in the node, adjacent the node and/or at least at a proximity thereto.

Abstract: An electronic module, more particularly a control module or sensor module for a motor vehicle transmission, has a circuit board having a first side and a second side facing away from the first side, electronic components arranged on the first side, and a casting compound arranged on the first side. The casting compound covers the electronic components. The circuit board has a through-hole connecting the first side to the second side. A sensor element covering the through-hole is arranged on the first side of the circuit board.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.

Abstract: An electrical node includes a substrate for accommodating a functional element. The substrate includes a first side and an opposite second side, and hosting a number of connecting elements. The functional element includes an electronic component and conductive traces. The electrical node also includes a first material layer defining a protective covering. The first material layer defining at least a portion of the exterior surface of the nod arranged to reduce at least thermal expansion and/or mechanical deformation related stresses between one or more elements included in the node, adjacent the node and/or at least at a proximity thereto.

Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.

Abstract: To obtain a power conversion device capable of reducing a loss of the power conversion device to improve fuel efficiency and electricity efficiency of an electrically driven vehicle. Provided is a power conversion device (1), which is to be mounted to a vehicle (VCL) configured to travel by using a drive motor (M1) as a motive power source. The power conversion device (1) includes inverters (100, 200) each configured to control the drive motor (M1) by having a plurality of switching elements (Q101 to Q106, Q201 to Q206) subjected to switching control. In the power conversion device (1), each of the plurality of switching elements (Q101 to Q106, Q201 to Q206) is formed of a wide band gap semiconductor.

Abstract: Devices and methods are provided for the separation and dispensing of material using a microfluidic separation column connected via an exit channel to one or more sheath flow channels. The flow of separated material through the separation column is at least partially driven by a voltage potential between a first electrode within the separation column and a terminating electrode within at least one of the sheath flow channels. The separation column, exit channel, sheath flow channels, and electrodes are all within a single monolithic chip. The presence of an on-chip terminating electrode allows for separated material to be entrained in the sheath fluids and ejected onto a surface that can be non-conductive. The presence of multiple sheath flows allows for sheath flow fluids to have different compositions from one another, while reducing the occurrence of sheath flow fluids entering the separation column.

Abstract: Disclosed is an optomechanical system (10) for capturing and transmitting incident light (40) with a variable direction of incidence to at least one collecting element (31, 31?, 31?, 31??, 31A, 31B), with an optical arrangement (20) able to capture a beam of the incident light (40), concentrate the captured beam of the incident light, and transmit one or more concentrated beams (50) of the incident light to the at least one collecting element (31, 31?, 31?, 31??, 31A, 31B), and a shifting mechanism for moving the optical arrangement (20) with respect to the at least one collecting element (31, 31?, 31?, 31??, 31A, 31B), wherein the moving of the shifting mechanism is controllable in such a way that, for any direction of incidence of the incident light (40), the one or more concentrated beams (50) of the incident light can be optimally collected by the at least one collecting element (31, 31?, 31?, 31??, 31A, 31B), In this optomechanical system (10), the optical arrangement (20) comprises a first optical la

Abstract: A manufacturing method for a solar cell is provided. The method includes: preparing a photoelectric converter which includes a light receiving surface and a back surface opposed to the light receiving surface and has n-type regions and p-type regions alternately arranged in a first direction on the back surface; forming a groove which is extended in the first direction on the light receiving surface after an electrode layer is formed on the n-type regions and the p-type regions; and dividing the photoelectric converter into a plurality of sub-cells along the groove.

Abstract: A control device for a pole-number switching electric motor applied to a system including an electric motor capable of switching a number of poles, and an inverter electrically connected to stator windings of the electric motor; includes: a basic operation unit configured to operate the inverter to control a current amplitude which is magnitude of a current vector flowing in the stator winding, and a switching operation unit configured to operate the inverter to reduce the current amplitude before switching and increase the current amplitude after switching. The switching operation unit, the pole number switching period, operates the inverter so that a total value of the current amplitude before switching and the current amplitude after switching does not exceed a limiting current value.

Abstract: A memory sub-system configured to use first values of a plurality of optimized read voltages to perform a first read calibration, which determines second values of the plurality of optimized read voltages. A plurality of shifts, from the first values to the second values respectively, can be computed for the plurality of optimized read voltages respectively. After recognizing a pattern in the plurality of shifts that are computed for the plurality of voltages respectively, the memory sub-system can control and/or initiate a second read calibration based on the recognized pattern in the shifts.

Abstract: A high-frequency module (1) includes a component (3a) mounted on an upper surface (2a) of a substrate (2), a second sealing resin layer (4) stacked on the upper surface (2a) of the substrate (2), a component (3b) mounted on a lower surface (2b) of the substrate (2), a first sealing resin layer (5) stacked on the lower surface (2b) of the substrate (2), and a first terminal assembly (6) and a second terminal assembly (7) that are mounted on the lower surface (2b) of the substrate (2). The first terminal assembly (6) is mounted on a four-corner portion of the substrate (2) and includes a connection conductor (6a) thicker than a connection conductor (7a) of the second terminal assembly (7).

Abstract: According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. Thea fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.

Abstract: A method of analyzing a molecule in a nanopore is disclosed. A voltage is applied across a nanopore that is inserted in a membrane by coupling the nanopore to a voltage source. The nanopore is decoupled from the voltage source. After the decoupling, a rate of decay of the voltage across the nanopore is determined. A molecule in the nanopore is distinguished from other possible molecules based on the determined rate of decay of the voltage across the nanopore.

Abstract: Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

Abstract: A driving device drives a motor having coils. The driving device includes a connection switching unit to switch a connection state of the coils, a temperature sensor to detect a room temperature, and a controller to switch the connection state of the coils based on a detected temperature by the temperature sensor.

Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprising performing a read operation of one or more memory cells neighboring a target memory cell, thereby determining a data pattern of the one or more neighboring memory cells, storing the data pattern and, during a program operation of the target memory cell, adjusting a verify voltage level according to the stored data pattern of the one or more neighboring memory cells.